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1 TMS320C6454 fixed-point digital signal processor 1.1 features TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 32-bit ddr2 memory controller (ddr2-533 high-performance fixed-point dsp (c6454) sdram) ? 1.39-, 1.17-, and 1-ns instruction cycle time edma3 controller (64 independent channels) ? 720-mhz, 850-mhz, and 1-ghz clock rate ? eight 32-bit instructions/cycle 32-/16-bit host-port interface (hpi) ? 8000 mips/mmacs (16-bits) 32-bit 33-/66-mhz, 3.3-v peripheral component ? commercial temperature [0c to 90c] interconnect (pci) master/slave interface conforms to pci specification 2.3 tms320c64x+? dsp core ? dedicated sploop instruction one inter-integrated circuit (i 2 c) bus ? compact instructions (16-bit) two mcbsps ? instruction set enhancements 10/100/1000 mb/s ethernet mac (emac) ? exception handling ? ieee 802.3 compliant tms320c64x+ megamodule l1/l2 memory ? supports multiple media independent architecture: interfaces (mii, gmii, rmii, and rgmii) ? 256k-bit (32k-byte) l1p program cache ? 8 independent transmit (tx) and [direct mapped] 8 independent receive (rx) channels ? 256k-bit (32k-byte) l1d data cache two 64-bit general-purpose timers, [2-way set-associative] configurable as four 32-bit timers ? 8m-bit (1048k-byte) l2 unified mapped 16 general-purpose i/o (gpio) pins ram/cache [flexible allocation] system pll and pll controller ? 256k-bit (32k-byte) l2 rom secondary pll and pll controller, dedicated ? time stamp counter to emac and ddr2 memory controller endianess: little endian, big endian ieee-1149.1 (jtag?) 64-bit external memory interface (emifa) boundary-scan-compatible ? glueless interface to asynchronous 697-pin ball grid array (bga) package memories (sram, flash, and eeprom) and (ztz or gtz suffix), 0.8-mm ball pitch synchronous memories (sbsram and zbt sram) 0.09- m m/7-level cu metal process (cmos) ? supports interface to standard sync 3.3-/1.8-/1.5-v i/os, 1.25-/1.2-v internal devices and custom logic (fpga, cpld, pin-compatible with the tms320c6455 asics, etc.) fixed-point digital signal processor ? 32m-byte total addressable external memory space please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this document. all trademarks are the property of their respective owners. product preview information concerns products in the copyright ? 2006?2006, texas instruments incorporated formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice. product preview www.ti.com
1.1.1 ztz/gtz bga package (bottom view) 1.2 description TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the TMS320C6454 devices are designed for a package temperature range of 0c to +90c (commercial temperature range). figure 1-1. ztz/gtz bga package (bottom view) the tms320c64x+? dsps (including the TMS320C6454 device) are the highest-performance fixed-point dsp generation in the tms320c6000? dsp platform. the c6454 device is based on the third-generation high-performance, advanced velociti? very-long-instruction-word (vliw) architecture developed by texas instruments (ti), making these dsps an excellent choice for applications including video and telecom infrastructure, imaging/medical, and wireless infrastructure (wi). the c64x+? devices are upward code-compatible from previous devices that are part of the c6000? dsp platform. the c6454 offers a lower cost pin-compatible migration path for c6455 customers who don't need the 2mb of the c6455 or the high-speed interconnect provided by serial rapidio. the c6454 also provides an excellent migration path for existing c6414/6415/6416 customers who require c6454 advanced peripherals; ddr2 at 533 mhz provides 2x performance boost over older sdram interface, gigabit ethernet provides low-cost high-performance ubiquitous packet interface, and 66-mhz pci (revision 2.3 complaint) provides legacy high-bandwidth interconnect. based on 90-nm process technology and with performance of up to 8000 million instructions per second (mips) [or 8000 16-bit mmacs per cycle] at a clock rate of 1 ghz, the c6454 device offers cost-effective solutions to high-performance dsp programming challenges. the c6454 dsp possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. TMS320C6454 fixed-point digital signal processor 2 submit documentation feedback www.ti.com product preview ztz/gtz 697-pin ball grid arra y (bga) p ackage ( bott om view ) a 2 b 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 27 28 29 ag ah aj note: the ztz mechanical package designator represents the version of the gtz package with lead-free balls. for more detailed information, see the mechanical data section of this document.
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the c64x+ dsp core employs eight functional units, two register files, and two data paths. like the earlier c6000 devices, two of these eight functional units are multipliers or .m units. each c64x+ .m unit doubles the multiply throughput versus the c64x core by performing four 16-bit x 16-bit multiply-accumulates (macs) every clock cycle. thus, eight 16-bit x 16-bit macs can be executed every cycle on the c64x+ core. at a 1-ghz clock rate, this means 8000 16-bit mmacs can occur every second. moreover, each multiplier on the c64x+ core can compute one 32-bit x 32-bit mac or four 8-bit x 8-bit macs every clock cycle. the c6454 dsp integrates a large amount of on-chip memory organized as a two-level memory system. the level-1 (l1) program and data memories on the c6454 device are 32kb each. this memory can be configured as mapped ram, cache, or some combination of the two. when configured as cache, l1 program (l1p) is a direct mapped cache where as l1 data (l1d) is a two-way set associative cache. the level 2 (l2) memory is shared between program and data space and is 1048kb in size. l2 memory can also be configured as mapped ram, cache, or some combination of the two. the c64x+ megamodule also has a 32-bit peripheral configuration (cfg) port, an internal dma (idma) controller, a system component with reset/boot control, interrupt/exception control, a power-down control, and a free-running 32-bit timer for time stamp. the peripheral set includes: an inter-integrated circuit bus module (i2c); two multichannel buffered serial ports (mcbsps); a user-configurable 16-bit or 32-bit host-port interface (hpi16/hpi32); a peripheral component interconnect (pci); a 16-pin general-purpose input/output port (gpio) with programmable interrupt/event generation modes; an 10/100/1000 ethernet media access controller (emac), which provides an efficient interface between the c6454 dsp core processor and the network; a management data input/output (mdio) module (also part of the emac) that continuously polls all 32 mdio addresses in order to enumerate all phy devices in the system; a glueless external memory interface (64-bit emifa), which is capable of interfacing to synchronous and asynchronous peripherals; and a 32-bit ddr2 sdram interface. the i2c ports on the c6454 allows the dsp to easily control peripheral devices and communicate with a host processor. in addition, the standard multichannel buffered serial port (mcbsp) may be used to communicate with serial peripheral interface (spi) mode peripheral devices. the c6454 has a complete set of development tools which includes: a new c compiler, an assembly optimizer to simplify programming and scheduling, and a windows? debugger interface for visibility into source code execution. submit documentation feedback TMS320C6454 fixed-point digital signal processor 3 product preview www.ti.com
1.3 functional block diagram TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 figure 1-2 shows the functional block diagram of the c6454 device. figure 1-2. functional block diagram TMS320C6454 fixed-point digital signal processor 4 submit documentation feedback www.ti.com product preview l2 memory controller (memory protect/ bandwidth mgmt) ddr2 mem ctlr system (b) c64x+ dsp core data path b b register file b31?b16 b15?b0 instruction fetch data path a a register file a31?a16 a15?a0 device configuration logic .l1 .s1 .m1 xxxx .d1 .d2 .m2 xxxx .s2 .l2 64 sbsram sram l1p cache direct-mapped 32k bytes l1d cache 2-way set-associative32k bytes t otal c6454 primary switched central resource pll1 and pll1 controller emifa zbt sram hi boot configuration rom/flash i/o devices i2c gpio16 (b) 16 mcbsp0 (a) internal dma (idma) me g a m o d u l e l2 cache memory 1048k bytes l1p memory controller (memory protect/bandwidth mgmt) mcbsp1 (a) hpi (32/16) (b) instruction decode 16-/32-bit instruction dispatch control registers in-circuit emulation ddr2 sdram 32 lo timer1 (c) hi lo timer0 (c) pll2 and pll2 controller (d) emac 10/100/1000 sploop buffer power control l1d memory controller (memory protect/bandwidth mgmt) interrupt and exception controller edma 3.0 l2 rom 32k bytes (e) secondary switched central resource a. mcbsps: framing chips ? h.100, mvip , scsa, t1, e1; ac97 devices; spi devices; codecs b. the pci peripheral pins are muxed with some of the hpi peripheral pins. for more detailed information, see the device configuration section of this document. c. each of the timer peripherals (timer1 and timer0) is configurable as either two 64-bit general-purpose timers or two 32-bit general-purpose timers or a watchdog timer . d. the pll2 controller also generates clocks for the emac. e. when accessing the internal rom of the dsp , the cpu frequency must always be less than 750 mhz. mdio rmgii (d) gmii rmii mii pci66 (b)
contents TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 1 TMS320C6454 fixed-point digital signal 5.5 megamodule resets ................................ 81 processor .................................................. 1 5.6 megamodule revision ............................... 82 1.1 features .............................................. 1 5.7 c64x+ megamodule register description(s) ........ 83 1.1.1 ztz/gtz bga package (bottom view) .............. 2 6 device operating conditions ........................ 90 1.2 description ............................................ 2 6.1 absolute maximum ratings over operating case temperature range (unless otherwise noted) ..... 90 1.3 functional block diagram ............................ 4 6.2 recommended operating conditions ............... 90 2 device overview ......................................... 6 6.3 electrical characteristics over recommended 2.1 device characteristics ................................ 6 ranges of supply voltage and operating case 2.2 cpu (dsp core) description ......................... 7 temperature (unless otherwise noted) ............ 92 2.3 memory map summary ............................. 10 7 c64x+ peripheral information and electrical 2.4 boot sequence ...................................... 12 specifications ........................................... 94 2.5 pin assignments .................................... 14 7.1 parameter information .............................. 94 2.6 signal groups description .......................... 18 7.2 recommended clock and control signal transition behavior ............................................. 96 2.7 terminal functions .................................. 24 7.3 power supplies ...................................... 96 2.8 development ........................................ 47 7.4 enhanced direct memory access (edma3) 3 device configuration .................................. 50 controller ............................................ 98 3.1 device configuration at device reset .............. 50 7.5 interrupts ........................................... 112 3.2 peripheral configuration at device reset ........... 52 7.6 reset controller .................................... 116 3.3 peripheral selection after device reset ............ 53 7.7 pll1 and pll1 controller ......................... 123 3.4 device state control registers ..................... 55 7.8 pll2 and pll2 controller ......................... 138 3.5 device status register description ................. 65 7.9 ddr2 memory controller .......................... 147 3.6 jtag id (jtagid) register description ............ 67 7.10 external memory interface a (emifa) ............. 149 3.7 pullup/pulldown resistors ........................... 67 7.11 i2c peripheral ...................................... 160 3.8 configuration examples ............................. 69 7.12 host-port interface (hpi) peripheral ............... 166 4 system interconnect ................................... 71 7.13 multichannel buffered serial port (mcbsp) ........ 177 4.1 internal buses, bridges, and switch fabrics ........ 71 7.14 ethernet mac (emac) ............................. 187 4.2 data switch fabric connections .................... 72 7.15 timers .............................................. 205 4.3 configuration switch fabric ......................... 74 7.16 peripheral component interconnect (pci) ......... 207 4.4 priority allocation .................................... 76 7.17 general-purpose input/output (gpio) ............. 214 5 c64x+ megamodule .................................... 77 7.18 ieee 1149.1 jtag ................................. 216 5.1 memory architecture ................................ 77 8 mechanical data ....................................... 217 5.2 memory protection .................................. 80 8.1 thermal data ...................................... 217 5.3 bandwidth management ............................ 80 8.2 packaging information ............................. 217 5.4 power-down control ................................ 81 revision history ............................................ 218 submit documentation feedback contents 5 product preview www.ti.com
2 device overview 2.1 device characteristics TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 2-1 , provides an overview of the c6454 dsp. the tables show significant features of the c6454 device, including the capacity of on-chip ram, the peripherals, the cpu frequency, and the package type with pin count. table 2-1. characteristics of the c6454 processor hardware features c6454 emifa (64-bit bus width) 1 (clock source = aeclkin or sysclk4) ddr2 memory controller (32-bit bus width) [1.8 v i/o] 1 (clock source = clkin2) edma3 (64 independent channels) [cpu/3 clock rate] 1 i2c 1 peripherals hpi (32- or 16-bit user selectable) 1 (hpi16 or hpi32) not all peripherals pins are available at the same pci (32-bit), [66-mhz or 33-mhz] 1 (pci66 or pci33) time (for more detail, see mcbsps (internal cpu/6 or external clock source up the device configuration 2 to 100 mbps) section). 10/100/1000 ethernet mac (emac) 1 management data input/output (mdio) 1 64-bit timers (configurable) 2 64-bit or 4 32-bit (internal clock source = cpu/6 clock frequency) general-purpose input/output port (gpio) 16 size (bytes) 1144k 32k-byte (32kb) l1 program memory controller [sram/cache] on-chip memory organization 32kb data memory controller [sram/cache] 1048kb l2 unified memory/cache 32kb l2 rom c64x+ megamodule megamodule revision id register (address location: see section 5.6 , megamodule revision revision id 0181 2000h) see section 3.6 , jtag id (jtagid) register jtag bsdl_id jtagid register (address location: 0x02a80008) description frequency mhz 720, 850, and 1000 (1 ghz) 1.39 ns (c6454-720), 1.17 ns (c6454-850), cycle time ns 1 ns (c6454-1000) [1 ghz cpu] 1.25 v (-1000) core (v) 1.2 v (-850/-720) voltage 1.5/1.8 [emac rgmii], and i/o (v) 1.8 and 3.3 v [i/o supply voltage] pll1 and pll1 clkin1 frequency multiplier bypass (x1), x15, x20, x25, x30, x32 controller options clkin2 frequency multiplier pll2 x20 [ddr2 memory controller and emac support only] 697-pin flip-chip plastic bga (ztz) bga package 24 x 24 mm 697-pin plastic bga (gtz) process technology m 0.09 m product preview (pp), advance information (ai), product status (1) pp or production data (pd) (1) product preview information concerns experimental products (designated as tmx) that are in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice. device overview 6 submit documentation feedback www.ti.com product preview
2.2 cpu (dsp core) description TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 2-1. characteristics of the c6454 processor (continued) hardware features c6454 tmx320c6454ztz7, (for more details on the c64x+? dsp part device part numbers tmx320c6454ztz8, numbering, see figure 2-12 ) tmx320c6454ztz the c64x+ central processing unit (cpu) consists of eight functional units, two register files, and two data paths as shown in figure 2-1 . the two general-purpose register files (a and b) each contain 32 32-bit registers for a total of 64 registers. the general-purpose registers can be used for data or can be data address pointers. the data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 lsbs of data placed in an even register and the remaining 8 or 32 msbs in the next upper register (which is always an odd-numbered register). the eight functional units (.m1, .l1, .d1, .s1, .m2, .l2, .d2, and .s2) are each capable of executing one instruction every clock cycle. the .m functional units perform all multiply operations. the .s and .l units perform a general set of arithmetic, logical, and branch functions. the .d units primarily load data from memory to the register file and store results from the register file into memory. the c64x+ cpu extends the performance of the c64x core through enhancements and new features. each c64x+ .m unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four 16 x 16 multiplies with add/subtract capabilities (including a complex multiply). there is also support for galois field multiplication for 8-bit and 32-bit data. many communications algorithms such as ffts and modems require complex multiplication. the complex multiply (cmpy) instruction takes for 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. there are also complex multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. the 32 x 32 bit multiply instructions provide the extended precision necessary for audio and other high-precision algorithms on a variety of signed and unsigned 32-bit data types. the .l or (arithmetic logic unit) now incorporates the ability to do parallel add/subtract operations on a pair of common inputs. versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data performing dual 16-bit add and subtracts in parallel. there are also saturated forms of these instructions. the c64x+ core enhances the .s unit in several ways. in the c64x core, dual 16-bit min2 and max2 comparisons were only available on the .l units. on the c64x+ core they are also available on the .s unit which increases the performance of algorithms that do searching and sorting. finally, to increase data packing and unpacking throughput, the .s unit allows sustained high performance for the quad 8-bit/16-bit and dual 16-bit instructions. unpack instructions prepare 8-bit data for parallel 16-bit operations. pack instructions return parallel results to output precision including saturation support. submit documentation feedback device overview 7 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 other new features include: sploop - a small instruction buffer in the cpu that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. the sploop buffer reduces the code size associated with software pipelining. furthermore, loops in the sploop buffer are fully interruptible. compact instructions - the native instruction size for the c6000 devices is 32 bits. many common instructions such as mpy, and, or, add, and sub can be expressed as 16 bits if the c64x+ compiler can restrict the code to use certain registers in the register file. this compression is performed by the code generation tools. instruction set enhancements - as noted above, there are new instructions such as 32-bit multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit galois field multiplication. exception handling - intended to aid the programmer in isolating bugs. the c64x+ cpu is able to detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and from system events (such as a watchdog time expiration). privilege - defines user and supervisor modes of operation, allowing the operating system to give a basic level of protection to sensitive resources. local memory is divided into multiple pages, each with read, write, and execute permissions. time-stamp counter - primarily targeted for real-time operating system (rtos) robustness, a free-running time-stamp counter is implemented in the cpu which is not sensitive to system stalls. for more details on the c64x+ cpu and its enhancements over the c64x architecture, see the following documents: tms320c64x/c64x+ dsp cpu and instruction set reference guide (literature number spru732 ) tms320c64x+ dsp cache user's guide (literature number spru862 ) tms320c64x+ megamodule reference guide (literature number spru871 ) tms320c6455 technical reference (literature number spru965 ) tms320c64x to tms320c64x+ cpu migration guide (literature number spraa84 ) device overview 8 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 figure 2-1. tms320c64x+? cpu (dsp core) data paths submit documentation feedback device overview 9 product preview www.ti.com src2 src2 .d1 .m1 .s1 .l1 long src odd dst src2 src1 src1src1 src1 even dsteven dst odd dst dst1 dst src2src2 src2 long src da1 st1bld1b ld1a st1a data path a odd register file a (a1, a3, a5...a31) odd register file b (b1, b3, b5...b31) .d2 src1 dst src2 da2 ld2a ld2b src2 .m2 src1 dst1 .s2 src1 even dst long src odd dst st2a st2b long src .l2 even dst odd dst src1 data path b control register 32 msb 32 lsb dst2 (a) 32 msb 32 lsb 2x1x 32 lsb 32 msb 32 lsb 32 msb dst2 (b) (b) (a) 8 8 8 8 32 32 32 32 (c) (c) even register file a (a0, a2, a4...a30) even register file b (b0, b2, b4...b30) (d) (d) (d) (d) a. on .m unit, dst2 is 32 msb. b. on .m unit, dst1 is 32 lsb. c. on c64x cpu .m unit, src2 is 32 bits; on c64x+ cpu .m unit, src2 is 64 bits. d. on .l and .s units, odd dst connects to odd register files and even dst connects to even register files.
2.3 memory map summary TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 2-2 shows the memory map address ranges of the c6454 device. the external memory configuration register address ranges in the c6454 device begin at the hex address location 0x7000 0000 for emifa and hex address location 0x7800 0000 for ddr2 memory controller. table 2-2. c6454 memory map summary memory block description block size (bytes) hex address range reserved 1024k 0000 0000 - 000f ffff internal rom 32k 0010 0000 - 0010 7fff reserved 7m - 32k 0010 8000 - 007f ffff internal ram (l2) [l2 sram] 1m 0080 0000 - 008f ffff reserved 5m 0090 0000 - 00df ffff l1p sram 32k 00e0 0000 - 00e0 7fff reserved 1m - 32k 00e0 8000 - 00ef ffff l1d sram 32k 00f0 0000 - 00f0 7fff reserved 1m - 32k 00f0 8000 - 00ff ffff reserved 8m 0100 0000 - 017f ffff c64x+ megamodule registers 4m 0180 0000 - 01bf ffff reserved 12.5m 01c0 0000 - 0287 ffff hpi control registers 256k 0288 0000 - 028b ffff mcbsp 0 registers 256k 028c 0000 - 028f ffff mcbsp 1 registers 256k 0290 0000 - 0293 ffff timer 0 registers 256k 0294 0000 - 0297 ffff timer 1 registers 128k 0298 0000 - 0299 ffff pll1 controller (including reset controller) registers 512 029a 0000 - 029a 01ff reserved 256k - 512 029a 0200 - 029b ffff pll2 controller registers 512 029c 0000 - 029c 01ff reserved 64k 029c 0200 - 029c ffff edma3 channel controller registers 32k 02a0 0000 - 02a0 7fff reserved 96k 02a0 8000 - 02a1 ffff edma3 transfer controller 0 registers 32k 02a2 0000 - 02a2 7fff edma3 transfer controller 1 registers 32k 02a2 8000 - 02a2 ffff edma3 transfer controller 2 registers 32k 02a3 0000 - 02a3 7fff edma3 transfer controller 3 registers 32k 02a3 8000 - 02a3 ffff reserved 256k 02a4 0000 - 02a7 ffff chip-level registers 256k 02a8 0000 - 02ab ffff device state control registers 256k 02ac 0000 - 02af ffff gpio registers 16k 02b0 0000 - 02b0 3fff i2c data and control registers 256k 02b0 4000 - 02b3 ffff reserved 720k 02b4 0000 - 02bf ffff pci control registers 256k 02c0 0000 - 02c3 ffff reserved 256k 02c4 0000 - 02c7 ffff emac control 4k 02c8 0000 - 02c8 0fff emac control module registers 2k 02c8 1000 - 02c8 17ff mdio control registers 2k 02c8 1800 - 02c8 1fff emac descriptor memory 8k 02c8 2000 - 02c8 3fff reserved 496k 02c8 4000 - 02cf ffff reserved 220m 02d0 0000 - 0fff ffff reserved 256m 1000 0000 - 1fff ffff device overview 10 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 2-2. c6454 memory map summary (continued) memory block description block size (bytes) hex address range reserved 256m 2000 0000 - 2fff ffff mcbsp 0 data 256 3000 0000 - 3000 00ff reserved 64m - 256 3000 0100 - 33ff ffff mcbsp 1 data 256 3400 0000 - 3400 00ff reserved 64m - 256 3400 0100 - 37ff ffff reserved 2k 3c00 0000 - 3c00 07ff reserved 16m - 2k 3c00 0800 - 3cff ffff reserved 48m 3d00 0000 - 3fff ffff pci external memory space 256m 4000 0000 - 4fff ffff reserved 256m 5000 0000 - 5fff ffff reserved 256m 6000 0000 - 6fff ffff emifa (emif64) configuration registers 128m 7000 0000 - 77ff ffff ddr2 memory controller configuration registers 128m 7800 0000 - 7fff ffff reserved 256m 8000 0000 - 8fff ffff reserved 256m 9000 0000 - 9fff ffff emifa ce2 - sbsram/async (1) 8m a000 0000 - a07f ffff reserved 256m - 8m a080 0000 - afff ffff emifa ce3 - sbsram/async (1) 8m b000 0000 - b07f ffff reserved 256m - 8m b080 0000 - bfff ffff emifa ce4 - sbsram/async (1) 8m c000 0000 - c07f ffff reserved 256m - 8m c080 0000 - cfff ffff emifa ce5 - sbsram/async (1) 8m d000 0000 - d07f ffff reserved 256m - 8m d080 0000 - dfff ffff ddr2 memory controller ce0 - ddr2 sdram 256m e000 0000 - efff ffff reserved 256m f000 0000 - ffff ffff (1) the emifa ce0 and ce1 are not functionally supported on the c6454 device, and therefore, are not pinned out. submit documentation feedback device overview 11 product preview www.ti.com
2.4 boot sequence 2.4.1 boot modes supported TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the boot sequence is a process by which the dsp's internal memory is loaded with program and data sections and the dsp's internal registers are programmed with predetermined values. the boot sequence is started automatically after each power-on reset, warm reset, and system reset. for more details on the initiators of these resets, see section 7.6 , reset controller. there are several methods by which the memory and register initialization can take place. each of these methods is referred to as a boot mode. the boot mode to be used is selected at reset through the bootmode[3:0] pins. each boot mode can be classified as a hardware boot mode or as a software boot mode. software boot modes require the use of the on-chip bootloader. the bootloader is dsp code that transfers application code from an external source into internal or external program memory after the dsp is taken out of reset. the bootloader is permanently stored in the internal rom of the dsp starting at byte address 0010 0000h. hardware boot modes are carried out by the boot configuration logic. the boot configuration logic is actual hardware that does not require the execution of dsp code. section 2.4.1 , boot modes supported, describes each boot mode in more detail. when accessing the internal rom of the dsp, the cpu frequency must always be less than 750 mhz. therefore, when using a software boot mode, care must be taken such that the cpu frequency does not exceed 750 mhz at any point during the boot sequence. after the boot sequence has completed, the cpu frequency can be programmed to the frequency required by the application. the c6454 has six boot modes: no boot (bootmode[3:0] = 0000b) with no boot, the cpu executes directly from the internal l2 sram located at address 0x80 0000. note: device operations is undefined if invalid code is located at address 0x80 0000. this boot mode is a hardware boot mode. host boot (bootmode[3:0] = 0001b and bootmode[3:0] = 0111b) if host boot is selected, after reset, the cpu is internally "stalled" while the remainder of the device is released. during this period, an external host can initialize the cpu's memory space as necessary through host port interface (hpi) or the peripheral component interconnect (pci) interface. internal configuration registers, such as those that control the emif can also be initialized by the host with two exceptions: device state control registers (section 3.4 ), pll1 and pll2 controller registers (section 7.7 and section 7.8 ) cannot be accessed through any host interface, including hpi and pci. once the host is finished with all necessary initialization, it must generate a dsp interrupt (dspint) to complete the boot process. this transition causes boot configuration logic to bring the cpu out of the "stalled" state. the cpu then begins execution from the internal l2 sram located at 0x80 0000. note that the dsp interrupt is registered in bit 0 (channel 0) of the edma event register (er). this event must be cleared by software before triggering transfers on dma channel 0. all memory, with the exceptions previously described, may be written to and read by the host. this allows for the host to verify what it sends to the dsp if required. after the cpu is out of the "stalled" state, the cpu needs to clear the dspint, otherwise, no more dspints can be received. as previously mentioned, for the c6454 device, the host port interface (hpi) and the peripheral component interconnect (pci) interface can be used for host boot. to use the hpi for host boot, the pci_en pin (y29) must be low [default] (enabling the hpi peripheral) and bootmode[3:0] must be set to 0001b at device reset. conversely, to use the pci interface for host boot, the pci_en pin (y29) must be high (enabling the pci peripheral) and bootmode[3:0] must be set to 0111b at device reset. for the hpi host boot, the dsp interrupt can be generated through the use of the dspint bit in the hpi control (hpic) register. for the hpi host boot, the cpu is actually held in reset until a dsp interrupt is generated by the host. the dsp interrupt can be generated through the use of the dspint bit in the hpi control (hpic) register. since the cpu is held in reset during hpi host boot, it will not respond to emulation software device overview 12 submit documentation feedback www.ti.com product preview
2.4.2 2nd-level bootloaders TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 such as code composer studio. for the pci host boot, the cpu is out of reset, but it executes an idle instruction until a dsp interrupt is generated by the host. the host can generate a dsp interrupt through the pci peripheral by setting the dspint bit in the back-end application interrupt enable set register (pcibintset) and the status set register (pcistatset). note that the hpi host boot is a hardware boot mode while the pci host boot is a software boot mode. if pci boot is selected, the on-chip bootloader configures the pll1 controller such that clkin1 is multiplied by 15. more specifically, pllm is set to 0eh (x15) and ratio is set to 0 (1) in the pll1 multiplier control register (pllm) and pll1 pre-divider register (prediv), respectively. the clkin1 frequency must not be greater than 50 mhz so that the maximum speed of the internal rom, 750 mhz, is not violated. the cfggp[2:0] pins must be set to 000b during reset for proper operation of the pci boot mode. as mentioned previously, a dsp interrupt must be generated at the end of the host boot process to begin execution of the loaded application. since the dsp interrupt generated by the hpi and pci is mapped to the edma event dsp_evt (dma channel 0), it will get recorded in bit 0 of the edma event register (er). this event must be cleared by software before triggering transfers on dma channel 0. emifa 8-bit rom boot (bootmode[3:0] = 0100b) after reset, the device will begin executing software out of an asynchronous 8-bit rom located in emifa ce3 space using the default settings in the emifa registers. this boot mode is a hardware boot mode. master i2c boot (bootmode[3:0] = 0101b) after reset, the dsp can act as a master to the i2c bus and copy data from an i2c eeprom or a device acting as an i2c slave to the dsp using a predefined boot table format. the destination address and length are contained within the boot table. this boot mode is a software boot mode. slave i2c boot (bootmode[3:0] = 0110b) a slave i2c boot is also implemented, which programs the dsp as an i2c slave and simply waits for a master to send data using a standard boot table format. using the slave i2c boot, a single dsp or a device acting as an i2c master can simultaneously boot multiple slave dsps connected to the same i2c bus. note that the master dsp may require booting via an i2c eeprom before acting as a master and booting other dsps. the slave i2c boot is a software boot mode. any of the boot modes can be used to download a 2nd-level bootloader. a 2nd-level bootloader allows for any level of customization to current boot methods as well as definition of a completely customized boot. ti offers a few 2nd-level bootloaders, such as an emac bootloader, which can be loaded using the master i2c boot. submit documentation feedback device overview 13 product preview www.ti.com
2.5 pin assignments 2.5.1 pin map TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 figure 2-2 through figure 2-5 show the c6454 pin assigments in four quadrants (a, b, c, and d). figure 2-2. c6454 pin map (bottom view) [quadrant a] device overview 14 submit documentation feedback www.ti.com product preview ag af ae ad ac abaa y w v u t r 13 12 11 10 9 8 7 6 5 4 3 2 1 13 12 11 10 9 8 7 6 5 4 3 2 1 clkr1/ gp[0] hd15/ ad15 hd2/ ad2 pgnt / gp[12] hd22/ ad22 dv dd33 rsv15 pidsel rsv16 hds1 / pserr hint / pframe dv dd33 hhwil/ pclk v ss hd12/ ad12 hd24/ ad24 rsv03 hd20/ ad20 hd18/ ad18 hd6/ ad6 hd16/ ad16 v ss hd28/ ad28 hd17/ ad17 hd31/ ad31 hd14/ ad14 hcntl1/ pdevsel hr/w / pcbe2 hrdy / pirdy prst / gp[13] hd21/ ad21 dv dd33 v ss emu8 rsv36 emu11 emu1 emu10 emu12 rsv37 emu15 emu4 emu13 dv dd33 dv dd33 v ss emu0 v ss dv dd33 rsv38 emu6 clkx1/ gp[3] dv dd33 v ss emu18 dv dd33 emu5 v ss dv dd33 hd9/ ad9 hd23/ ad23 hd3/ ad3 hd10/ ad10 gp[6] v ss emu14 gp[7] rsv02 hd4/ ad4 hd30/ ad30 cv dd hd27/ ad27 v ss v ss v ss dv dd33 v ss cv dd cv dd v ss dv dd33 dv dd33 v ss v ss dv dd33 v ss v ss hd19/ ad19 hd13/ ad13 hd29/ ad29 dv dd33 dv dd33 hd25/ ad25 dv dd33 hd0/ ad0 v ss hd11/ ad11 toutl0 emu3 emu7 toutl1 v ss dv dd33 v ss dv dd33 v ss hds2 / pcbe1 hcntl0/ pstop hcs / pperr v ss hd8/ ad8 v ss hd26/ ad26 v ss hd7/ ad7 hd1/ ad1 emu2 rsv39 v ss dv dd33 has / ppar hd5/ ad5 ah tinpl0 emu17 tdo nmi emu16 gp[4] v ss trst tdi rsv27 emu9 aj tinpl1 tms v ss clks rsv40 gp[5] dv dd33 dv dd33 tck rsv26 sysclk4/ gp[1] 14 v ss dv dd33 resetstat por v ss cv dd cv dd reset dv dd33 v ss 15 rsv64 v ss dv dd33 rsv45 cv dd v ss v ss rsv46 v ss dv dd33 14 15 v ss cv dd cv dd cv dd v ss v ss v ss cv dd rsv68 v ss v ss cv dd agaf ae ad ac ab aa y w v u t r ah aj fsx0 dr0 fsr0 dr1/ gp[8] clkr0 fsx1/ gp[11] dx1/ gp[9] clkx0 dx0 fsr1/ gp[10]
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 figure 2-3. c6454 pin map (bottom view) [quadrant b] submit documentation feedback device overview 15 product preview www.ti.com agaf ae ad ac ab aa y w v u t r 17 18 19 20 21 22 23 24 25 26 27 28 29 17 18 19 20 21 22 23 24 25 26 27 28 29 sda aed27 v ss asads / asre aed17 ahold pllv1 aea13/ lendian aea4/ sysclkout _en aea5/ mcbsp1 _en aea6/pci66 aeclkout ace5 ace4 aba0/ ddr2_en abe7 ace2 rsv41 aaoe / asoe rsv42 rsv44 abe2 abe0 aed29 aed31 ace3 aea1/ cfggp1 aea11 aea2/ cfggp2 aea14/ hpi_ width aed21 dv dd33 v ss v ss v ss dv dd33 rsv73 rsv63 v ss v ss rsv17 v ss dv dd33 v ss v ss rsv74 rsv50 dv dd33 v ss dv dd33 v ss aed3 v ss rsv49 aed7 aed1 scl rsv65 v ss rsv72 rsv48 v ss dv dd33 v ss aed25 aed28 aed11 aed4 aed9 aed15 rsv47 aed16 aba1/ emifa_en rsv43 abe1 rsv71 aed24 dv dd33 v ss v ss aed19 dv dd33 cv dd cv dd dv dd33 v ss v ss dv dd33 dv dd33 v ss v ss v ss dv dd33 v ss aed26 v ss dv dd33 aed22 aed0 aed13 aed12 aed10 rsv54 rsv75 rsv51 aed30 dv dd33 aea12 v ss v ss v ss v ss rsv20 aea0/ cfggp0 v ss dv dd33 ar/w dv dd33 pci_en dv dd33 aed23 aawe / aswe rsv53 rsv52 dv dd33 abe3 aea3 aed8 ah dv dd33 v ss rsv76 rsv58 aed14 rsv55 aed2 aed18 v ss rsv62 v ss v ss v ss rsv59 aj v ss dv dd33 v ss rsv57 aed5 rsv56 aed6 aed20 dv dd33 rsv78 rsv61 rsv60 rsv77 16 v ss rsv66 v ss dv dd33 v ss rsv70 cv dd v ss dv dd33 v ss 16 v ss cv dd cv dd rsv69 v ss v ss v ss rsv67 v ss cv dd ag af ae adac abaa y w v u t r ah aj
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 figure 2-4. c6454 pin map (bottom view) [quadrant c] device overview 16 submit documentation feedback www.ti.com product preview c d e f g h j k l m n p 17 18 19 20 21 22 23 24 25 26 27 28 29 17 18 19 20 21 22 23 24 25 26 27 28 29 rsv09 aed52 dv dd33 v ss v ss v ss aeclkin aea9/ macsel0 clkin1 dv dd33 aea15/ aeclkin _sel aed40 aed44 aed42 aed34 abe6 aed32 abe4 aea18/ boot mode2 aed37 abusreq aed46 aea16/ boot mode0 aea19/ boot mode3 aholda aea10/ macsel1 v ss v ss dv dd18 ded19 v ss cv dd v ss dsddqs2 dsddq gate2 ded23 dv dd18 dv dd33 dsddqs3dsddqs3 v ss dv dd18 rsv11 rsv12 rsv33 dsddqm2 ded26 v ss rsv32 rsv23 v ss v ss dea4 dea1 av dll2 dv dd33 dv dd33 aed56 aed50 aed45 aed59aed61 aed58 dea5 aed60 aed33 aea17/ boot mode1 dsddq gate3 rsv19 aed55 v ss dv dd18 dv dd18 aed39 dv dd33 v ss v ss rsv30 dv dd33 v ss v ss dv dd18 v ss dv dd18 dv dd18 aed35 aed48 aed54 dv dd18 v ss dv dd33 aed47 dv dd33 dv dd33 aed57 ded27 dsddqs2 dea0 aed41 dsddqm3 dv dd33 v ss cv dd v ss cv dd v ss aea8/ pci_eeai rsv31 aed38 v ss aardy v ss aed36 aed63 v ss ded22 ded18 dea6 abe5 aea7 aed43 b ded29 ded31 dv dd18 ded25 rsv22 dea2 aed49 aed51 v ss dv dd18 ded21 ded16 dea7 a ded28 ded30 v ss ded24 dv dd18mon dea3 aed62 aed53 dv dd33 v ss ded20 ded17 deodt1 16 dv dd18 cv dd deodt0 dea8 cv dd v ss v ss dea9 dea10 dea11 16 cv dd v ss v ss cv dd v ss cv dd c d e f g h j k l m n pb a
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 figure 2-5. c6454 pin map (bottom view) [quadrant d] submit documentation feedback device overview 17 product preview www.ti.com a d e f g h j k l m n p 13 12 11 10 9 8 7 6 5 4 3 2 1 13 12 11 10 9 8 7 6 5 4 3 2 1 rgrxd2 rgtxd3 dv dd33 mtxd2 v ss mtxd0/ rmtxd0 cv ddmon mtxd6 v ss preq / gp[15] pinta / gp[14] mrxd2 mrxd3 mrxd0/ rmrxd0 v ss mtxd3 mcol mrxd5 mtxd1/ rmtxd1 dv dd15 mtxd4 mcrs/ rmcrsdv ptrdy mtxd7 mtclk/ rmrefclk mdclk rgrxd3 dv dd18 ded1 dsddqs0 dsddqm0 ded2 dsddqs0 ded6 ded7 ded8 ded9 ded10 dsddqm1 dsddqs1 ded15 ded14 v ss rsv25 rsv35 rsv34 v ss dv dd15 v ss v ss dv dd15 v ss v ss dsdwe dsdras dsdcas v ss ded3 rsv29 dv dd33 rgtxd0 rgtxd1 rgrefclk rgtxctl dv dd15mon rgrxd1 rsv18 rsv13 gmtclk mtxd5 dsddq gate0 ded0 dv dd15 ded12 dv dd18 ded5 rgrxd0 dv dd33 v ss v ss v ss dv dd33mon v ss rsv21 ded13 ded4 v ss av dll1 v ss v refhstl rgmdclk rsv24 dsddq gate1 rgrxctl v ss dv dd15 rgtxc rgrxc dsddqs1 dv dd18 dv dd18 rsv14 dv dd18 mrxd7 v ss cv dd rsv28 cv dd pcbe0 / gp[2] pcbe3 dv dd33 mtxen/ rmtxen v ss dv dd33 v ss rgmdio pllv2 v ss ded11 dv dd18 dv dd18 mrxd4 mdio rgtxd2 b dv dd15 v ss dv dd18 dv dd18 rsv07 dv dd18 clkin2 dv dd33 v ss v ss v ss v ss v ss c v ss mrxdv mrxer/ rmrxer cv dd mrxd1/ rmrxd1 mrxd6 mrclk dv dd15 v ss v ss 14 ddr2 clkout v refsstl dsdcke dce0 cv dd ddr2 clkout v ss v ss dv dd18 cv dd 15 dea13 dba0 dba1 dba2 v ss dea12 cv dd dv dd18 v ss v ss 14 15 cv dd rsv04 v ss cv dd v ss cv dd rsv05 fd ea g h j k l m n pb c
2.6 signal groups description TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 figure 2-6. cpu and peripheral signals device overview 18 submit documentation feedback www.ti.com product preview trst ieee standard 1149.1 (jtag) emulation reserved reset and interrupts control/status tdi tdo tms tck nmi reset rsv03 rsv04 clock/pll1 and pll controller clkin1 emu0emu1 sysclk4/gp[1] (a) emu14emu15 emu16 emu17 rsv02 emu18 rsv06 rsv07 rsv05 rsv77 rsv78 rsv76 ?? ? ?? ? resetstat clkin2 por pci_en peripheral enable/disable clock/pll2 pllv2 pllv1 a. this pin functions as gp[1] by default. for more details, see the device configuration section of this document.
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 figure 2-7. timers/gpio peripheral signals submit documentation feedback device overview 19 product preview www.ti.com a. this pin functions as gp[1] by default. for more details, see the device configuration section of this document. b. these mcbsp1 peripheral pins are muxed with the gpio peripheral pins and by default these signals function as gpio peripheral pins. for more details, see the device configuration section of this document. c. these pci peripheral pins are muxed with the gpio peripheral pins and by default these signals function as gpio peripheral pins. for more details, see the device configuration section of this document. gpio general-purpose input/output 0 (gpio) port clkx1/gp[3] (b) pcbe0 /gp[2] (c) sysclk4/gp[1] (a) preq /gp[15] (c) pinta /gp[14] (c) prst /gp[13] (c) pgnt /gp[12] (c) fsx1/gp[11] (b) fsr1/gp[10] (b) dx1/gp[9] (b) dr1/gp[8] (b) gp[7]gp[6] gp[5] gp[4] clkr1/gp[0] (b) t imers (64-bit) tinpl1 t imer 1 t imer 0 toutl1 tinpl0 toutl0
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 figure 2-8. emifa/ddr2 memory controller peripheral signals device overview 20 submit documentation feedback www.ti.com product preview ace4 (a) aeclkout aed[63:0] ace3 (a) ace2 (a) aea[19:0] aardy data memory map space select address byte enables 64 20 external memory i/f control emif a (64-bit data bus) aeclkin ahold aholda abusreq bus arbitration abe3 abe2 abe1 abe0 aswe /aawe ddr2clkout ded[31:0] dce0 dea[13:0] data memory map space select address byte enables 32 14 external memory i/f control ddr2 memoty controller (32-bit data bus) dsdcas dsdcke ddr2clkout dsddqs[3:0] dsdras dsdwe dsddqs[3:0] abe7 abe6 abe5 abe4 ace5 (a) bank address aba[1:0] ar/w aaoe /asoe asads /asre bank address dba[2:0] deodt[1:0] dsddqgate[0] dsddqm3 dsddqm2 dsddqm1 dsddqm0 a. the emif a ace0 and ace1 are not functionally supported on the c6454 device. dsddqgate[1] dsddqgate[2] dsddqgate[3]
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 figure 2-9. hpi/mcbsp/i2c peripheral signals submit documentation feedback device overview 21 product preview www.ti.com mcbsps (multichannel buffered serial ports) (b) clkx0fsx0 dx0 clkr0 fsr0 dr0 transmit mcbsp0 receive clock clkx1/gp[3] fsx1/gp[11] dx1/gp[9] clkr1/gp[0] fsr1/gp[10] dr1/gp[8] transmit mcbsp1 receive clock hhwil/pclk hcntl0/pstop hcntl1/pdevsel data register select half-word select control hpi (a) (host-port interface) 32 has /ppar hr/w /pcbe2 hcs /pperr hds1 /pserr hds2 /pcbe1 hrdy /pirdy hint /pframe (hpi16 onl y) hd[15:0]/ad[15:0] hd[31:16]/ad[31:16] scl i2c sda a. these hpi pins are muxed with the pci peripheral. by default, these pins function as hpi. when the hpi is enabled, the number of hpi pins used depends on the hpi configuration (hpi16 or hpi32). for more details on these muxed pins, see the device configuration section of this document. b. these mcbsp1 peripheral pins are muxed with the gpio peripheral pins and by default these signals function as gpio peripheral pins. for more details, see the device configuration section of this document. clks (shared)
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 figure 2-10. emac/mdio [mii/rmii/gmii/rgmii] peripheral signals device overview 22 submit documentation feedback www.ti.com product preview rgtxctl, rgrxctl mrxer/rmrxer, mrxdv, mcrs/rmcrsdv, mcol, mtxen/rmtxen ethernet mac (emac) and mdio mdiomdclk mdio clock clocks error detect and control input/output receive rgmdio rgmdclk rgtxd[3:0] a. rgmii signals are mutually exclusive to all other emac signals. rgtxc, rgrxc, rgrefclk mtxd[7:2], mtxd[1:0]/rmtxd[1:0] transmit rgmii (a) gmii rmii mii rgrxd[3:0] mrxd[7:2], mrxd[1:0]/rmrxd[1:0] rgmii (a) gmii rmii mii rgmii (a) gmii rmii mii rgmii (a) gmii rmii mii rgmii (a) gmii rmii mii gmii rmii mii rgmii (a) mtclk/rmrefclk, mrclk, gmtclk ethernet mac (emac)
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 figure 2-11. pci peripheral signals submit documentation feedback device overview 23 product preview www.ti.com hd[15:0]/ad[15:0] hr/w /pcbe2 hds2 /pcbe1 pcbe0 /gp[2] hhwil/pclkhint /pframe pinta /gp[14] data/address arbitration 32 clock control pci interface (a) has /ppar prst /gp[13] hrdy /pirdy hcntl0/pstop ptrdy pcbe3 pidselhcntl1/pdevsel hds1 /pserr error command byte enable hcs /pperr pgnt /gp[12] preq /gp[15] hd[31:16]/ad[31:16] a. these pci pins are muxed with the hpi or gpio peripherals. by default, these signals function as hpi or gpio or emac. for more details on these muxed pins, see the device configuration section of this document.
2.7 terminal functions TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the terminal functions table (table 2-3 ) identifies the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type (i, o/z, or i/o/z), whether the pin has any internal pullup/pulldown resistors, and a functional pin description. for more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and pullup/pulldown resistors, see section 3 , device configuration. table 2-3. terminal functions signal type (1) ipd/ipu (2) description name no. clock/pll configurations clkin1 n28 i ipd clock input for pll1. clkin2 g3 i ipd clock input for pll2. pllv1 t29 a 1.8-v i/o supply voltage for pll1 pllv2 a5 a 1.8-v i/o supply voltage for pll2 sysclk4 is the clock output at 1/8 of the device speed ( o/z) or this pin can be sysclk4/gp[1] (3) aj13 i/o/z ipd programmed as the gp1 pin ( i/o/z) [default]. jtag emulation tms aj10 i ipu jtag test-port mode select tdo ah8 o/z ipu jtag test-port data out tdi ah9 i ipu jtag test-port data in tck aj9 i ipu jtag test-port clock jtag test-port reset. for ieee 1149.1 jtag compatibility, see the ieee trst ah7 i ipd 1149.1 jtag compatibility statement portion of this document. emu0 (4) af7 i/o/z ipu emulation pin 0 emu1 (4) ae11 i/o/z ipu emulation pin 1 emu2 ag9 i/o/z ipu emulation pin 2 emu3 af10 i/o/z ipu emulation pin 3 emu4 af9 i/o/z ipu emulation pin 4 emu5 ae12 i/o/z ipu emulation pin 5 emu6 ag8 i/o/z ipu emulation pin 6 emu7 af12 i/o/z ipu emulation pin 7 emu8 af11 i/o/z ipu emulation pin 8 emu9 ah13 i/o/z ipu emulation pin 9 emu10 ad10 i/o/z ipu emulation pin 10 emu11 ad12 i/o/z ipu emulation pin 11 emu12 ae10 i/o/z ipu emulation pin 12 emu13 ad8 i/o/z ipu emulation pin 13 emu14 af13 i/o/z ipu emulation pin 14 emu15 ae9 i/o/z ipu emulation pin 15 emu16 ah12 i/o/z ipu emulation pin 16 emu17 ah10 i/o/z ipu emulation pin 17 emu18 ae13 i/o/z ipu emulation pin 18 resets, interrupts, and general-purpose input/outputs reset ag14 i device reset (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for most systems, a 1-k w resistor can be used to oppose the ipu/ipd. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.7 , pullup/pulldown resistors. (3) these pins are multiplexed pins. for more details, see section 3 , device configuration. (4) the c6454 dsp does not require external pulldown resistors on the emu0 and emu1 pins for normal or boundary-scan operation. device overview 24 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 2-3. terminal functions (continued) signal type (1) ipd/ipu (2) description name no. nonmaskable interrupt, edge-driven (rising edge) any noise on the nmi pin may trigger an nmi interrupt; therefore, if the nmi pin nmi ah4 i ipd is not used, it is recommended that the nmi pin be grounded versus relying on the ipd. resetstat ae14 o reset status pin. the resetstat pin indicates when the device is in reset por af14 i power on reset. gp[7] ag2 i/o/z ipd gp[6] ag3 i/o/z ipd general-purpose input/output (gpio) pins ( i/o/z). gp[5] aj2 i/o/z ipd gp[4] ah2 i/o/z ipd preq/gp[15] p2 i/o/z pinta (5) /gp[14] p3 i/o/z pci peripheral pins or general-purpose input/output (gpio) [15:12, 2] pins prst/gp[13] r5 i/o/z ( i/o/z) [default] pgnt/gp[12] r4 i/o/z pci bus request ( o/z) or gp[15] ( i/o/z) [default] pci interrupt a ( o/z) or gp[14] ( i/o/z) [default] fsx1/gp[11] ag4 i/o/z ipd pci reset ( i) or gp[13] ( i/o/z) [default] fsr1/gp[10] ae5 i/o/z ipd pci bus grant ( i) or gp[12] ( i/o/z) [default] pci command/byte enable 0 ( i/o/z) or gp[2] ( i/o/z) [default] dx1/gp[9] ag5 i/o/z ipd dr1/gp[8] ah5 i/o/z ipd mcbsp1 transmit clock ( i/o/z) or gp[3] ( i/o/z) [default] mcbsp1 receive clock ( i/o/z) or gp[0] ( i/o/z) [default] clkx1/gp[3] af5 i/o/z ipd gp[1] pin ( i/o/z). sysclk4 is the clock output at 1/8 of the device speed ( o/z) pcbe0/gp[2] p1 i/o/z or this pin can be programmed as a gp[1] pin ( i/o/z) [default]. sysclk4/gp[1] (3) aj13 o/z ipd clkr1/gp[0] af4 i/o/z ipd host-port interface (hpi) or peripheral component interconnect (pci) pci enable pin. this pin controls the selection (enable/disable) of the hpi and gp[15:8], or pci peripherals. this pin works in conjunction with the pci_en y29 i ipd mcbsp 1_en (aea5 pin) to enable/disable other peripherals (for more details, see section 3 , device configuration). hint/ pframe u3 i/o/z host interrupt from dsp to host ( o/z) or pci frame ( i/o/z) host control - selects between control, address, or data registers ( i) [default] or hcntl1/ pdevsel u4 i/o/z pci device select ( i/o/z) host control - selects between control, address, or data registers ( i) [default] or hcntl0/ pstop u5 i/o/z pci stop ( i/o/z) host half-word select - first or second half-word (not necessarily high or low hhwil/pclk v3 i/o/z order) [for hpi16 bus width selection only] ( i) [default] or pci clock ( i) hr/ w/ pcbe2 t5 i/o/z host read or write select ( i) [default] or pci command/byte enable 2 ( i/o/z) has/ppar t3 i/o/z host address strobe ( i) [default] or pci parity ( i/o/z) hcs/ pperr u6 i/o/z host chip select ( i) [default] or pci parity error ( i/o/z) hds1/ pserr (5) u2 i/o/z host data strobe 1 ( i) [default] or pci system error ( i/o/z) hds2/ pcbe1 u1 i/o/z host data strobe 2 ( i) [default] or pci command/byte enable 1 ( i/o/z) hrdy/ pirdy t4 i/o/z host ready from dsp to host ( o/z) [default] or pci initiator ready ( i/o/z) preq/gp[15] p2 i/o/z pci bus request ( o/z) or gp[15] ( i/o/z) [default] pinta (5) /gp[14] p3 i/o/z pci interrupt a ( o/z) or gp[14] ( i/o/z) default] prst/gp[13] r5 i/o/z pci reset ( i) or gp[13] ( i/o/z) [default] pgnt/gp[12] r4 i/o/z pci bus grant ( i) or gp[12] ( i/o/z)[default] pcbe0/gp[2] p1 i/o/z pci command/byte enable 0 ( i/o/z) or gp[2] ( i/o/z)[default] pcbe3 p5 i/o/z pci command/byte enable 3 ( i/o/z). by default, this pin has no function. pidsel r3 i pci initialization device select ( i). by default, this pin has no function. (5) these pins function as open-drain outputs when configured as pci pins. submit documentation feedback device overview 25 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 2-3. terminal functions (continued) signal type (1) ipd/ipu (2) description name no. ptrdy p4 i/o/z pci target ready ( prtdy) ( i/o/z). by default, this pin has no function. hd31/ad31 aa3 hd30/ad30 aa5 hd29/ad29 ac4 hd28/ad28 aa4 hd27/ad27 ac5 hd26/ad26 y1 hd25/ad25 ad2 hd24/ad24 w1 host-port data [31:16] pin ( i/o/z) [default] or pci data-address bus [31:16] i/o/z ( i/o/z) hd23/ad23 ac3 hd22/ad22 ae1 hd21/ad21 ad1 hd20/ad20 w2 hd19/ad19 ac1 hd18/ad18 y2 hd17/ad17 ab1 hd16/ad16 y3 hd15/ad15 ab2 hd14/ad14 w4 hd13/ad13 ac2 hd12/ad12 v4 hd11/ad11 af3 hd10/ad10 ae3 hd9/ad9 ab3 hd8/ad8 w5 i/o/z host-port data [15:0] pin ( i/o/z) [default] or pci data-address bus [15:0] ( i/o/z) hd7/ad7 ab4 hd6/ad6 y4 hd5/ad5 ad3 hd4/ad4 y5 hd3/ad3 ad4 hd2/ad2 w6 hd1/ad1 ab5 hd0/ad0 ae2 emifa (64-bit) - control signals common to all types of memory aba1/emifa_en v25 o/z ipd emifa bank address control (aba[1:0]) active-low bank selects for the 64-bit emifa. when interfacing to 16-bit asynchronous devices, aba1 carries bit 1 of the byte address. for an 8-bit asynchronous interface, aba[1:0] are used to carry bits 1 and 0 of the byte address ddr2 memory controller enable (ddr2_en) [ aba0] aba0/ddr2_en v26 o/z ipd 0 - ddr2 memory controller peripheral pins are disabled (default) 1 - ddr2 memory controller peripheral pins are enabled emifa enable (emifa_en) [ aba1] 0 - emifa peripheral pins are disabled (default) 1 - emifa peripheral pins are enabled device overview 26 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 2-3. terminal functions (continued) signal type (1) ipd/ipu (2) description name no. ace5 v27 o/z ipu emifa memory space enables ace4 v28 o/z ipu enabled by bits 28 through 31 of the word address ace3 w26 o/z ipu only one pin is asserted during any external data access note: the c6454 device does not have ace0 and ace1 pins ace2 w27 o/z ipu abe7 w29 o/z ipu abe6 k26 o/z ipu abe5 l29 o/z ipu emifa byte-enable control abe4 l28 o/z ipu decoded from the low-order address bits. the number of address bits or byte enables used depends on the width of external memory. abe3 aa29 o/z ipu byte-write enables for most types of memory. abe2 aa28 o/z ipu abe1 aa25 o/z ipu abe0 aa26 o/z ipu emifa (64-bit) - bus arbitration aholda n26 o ipu emifa hold-request-acknowledge to the host ahold r29 i ipu emifa hold request from the host abusreq l27 o ipu emifa bus request output emifa (64-bit) - asynchronous/synchronous memory control emifa external input clock. the emifa input clock (aeclkin or sysclk4 aeclkin n29 i ipd clock) is selected at reset via the pullup/pulldown resistor on the aea[15] pin. note: aeclkin is the default for the emifa input clock. aeclkout v29 o/z ipd emifa output clock [at emifa input clock (aeclkin or sysclk4) frequency] asynchronous memory write-enable/programmable synchronous interface aawe/ aswe ab25 o/z ipu write-enable aardy k29 i ipu asynchronous memory ready input ar/ w w25 o/z ipu asynchronous memory read/write aaoe/ asoe y28 o/z ipu asynchronous/programmable synchronous memory output-enable programmable synchronous address strobe or read-enable for programmable synchronous interface, the r_enable field in the chip select x configuration register selects between asads and asre: asads/ asre r26 o/z ipu ? if r_enable = 0, then the asads/ asre signal functions as the asads signal. ? if r_enable = 1, then the asads/ asre signal functions as the asre signal. submit documentation feedback device overview 27 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 2-3. terminal functions (continued) signal type (1) ipd/ipu (2) description name no. emifa (64-bit) - address aea19/bootmode3 n25 emifa external address (word address) ( o/z) controls initialization of the dsp modes at reset ( i) via pullup/pulldown resistors aea18/bootmode2 l26 [for more detailed information, see section 3 , device configuration.] aea17/bootmode1 l25 note: if a configuration pin must be routed out from the device, the internal o/z ipd pullup/pulldown (ipu/ipd) resistor should not be relied upon; ti recommends aea16/bootmode0 p26 the use of an external pullup/pulldown resistor. aea15/aeclkin_sel p27 boot mode - device boot mode configurations (bootmode[3:0]) [ note: aea14/hpi_width r25 the peripheral must be enabled to use the particular boot mode.] aea13/lendian r27 o/z ipu aea[19:16]: 0000 - no boot (default mode) aea12 r28 0001 - host boot (hpi) 0010 -reserved 0011 - reserved 0100 - emifa 8-bit rom boot 0101 - master i2c boot 0110 - slave i2c boot 0111 - host boot (pci) 1000 thru 1111 - reserved for more detailed information on the boot modes, see section 2.4 , boot sequence. cfggp[2:0] pins must be set to 000b during reset for proper operation of the pci boot mode. emifa input clock source select clock mode select for emifa (aeclkin_sel) aea15: 0 - aeclkin (default mode) o/z ipd 1 - sysclk4 (cpu/x) clock rate. the sysclk4 clock rate is software aea11 t25 selectable via the software pll1 controller. by default, sysclk4 is selected as cpu/8 clock rate. hpi peripheral bus width (hpi_width) select [applies only when hpi is enabled; pci_en pin = 0] aea14: 0 - hpi operates as an hpi16 (default). (hpi bus is 16 bits wide. hd[15:0] pins are used and the remaining hd[31:16] pins are reserved pins in the hi-z state.) 1 - hpi operates as an hpi32. device endian mode (lendian) aea13: 0 - system operates in big endian mode 1 - system operates in little endian mode(default) note: for proper c6454 device operation, the aea12 and aea11 pins must be externally pulled down with a 1-k w resistor at device reset. device overview 28 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 2-3. terminal functions (continued) signal type (1) ipd/ipu (2) description name no. aea10/macsel1 m25 emac/mdio interface select bits (macsel[1:0]) there are two configuration pins ? macsel[1:0] ? to select the aea9/macsel0 m27 emac/mdio interface. aea8/pci_eeai p25 aea[10:9]: macsel[1:0] aea7 n27 00 - 10/100 emac/mdio mii mode interface (default) 01 - 10/100 emac/mdio rmii mode interface aea6/pci66 u27 10 - 10/100/1000 emac/mdio gmii mode interface aea5/mcbsp1_en u28 11 - 10/100/1000 with rgmii mode interface aea4/ [rgmii interface requires a 1.8 v or 1.5 v i/o supply] t28 sysclkout_en pci i2c eeprom auto-initialization (pci_eeai) aea3 t27 aea8: pci auto-initialization via external i2c eeprom if the pci peripheral is disabled (pci_en pin = 0), this pin must not be aea2/cfggp2 t26 pulled up. aea1/cfggp1 u26 0 - pci auto-initialization through i2c eeprom is disabled (default). 1 - pci auto-initialization through i2c eeprom is enabled. pci frequency selection (pci66) [the pci peripheral needs be enabled (pci_en = 1) to use this function] selects the pci operating frequency of 66 mhz or 33 mhz pci operating frequency is selected at reset via the pullup/pulldown resistor on the pci66 pin: aea6: o/z ipd 0 - pci operates at 33 mhz (default). 1 - pci operates at 66 mhz. note: if the pci peripheral is disabled (pci_en = 0), this pin must not be pulled up. mcbsp1 enable bit (mcbsp1_en) selects which function is enabled on the mcbsp1/gpio muxed pins aea5: aea0/cfggp0 u25 0 - gpio pin functions enabled (default). 1 - mcbsp1 pin functions enabled. sysclkout enable bit (sysclkout_en) selects which function is enabled on the sysclk4/gp[1] muxed pin aea4: 0 - gp[1] pin function of the sysclk4/gp[1] pin enabled (default). 1 - sysclk4 pin function of the sysclk4/gp[1] pin enabled. configuration gpi (cfggp[2:0]) ( aea[2:0]) these pins are latched during reset and their values are shown in the devstat register. these values can be used by software routines for boot operations. aea3: for proper c6454 device operation, the aea3 pin must be pulled down to v ss with a 1-k w resistor at device reset. submit documentation feedback device overview 29 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 2-3. terminal functions (continued) signal type (1) ipd/ipu (2) description name no. emifa (64-bit) - data aed63 f25 aed62 a27 aed61 c27 aed60 c28 aed59 e27 aed58 d28 aed57 d27 aed56 f27 aed55 g25 aed54 g26 aed53 a28 aed52 f28 aed51 b28 aed50 g27 aed49 b27 aed48 g28 aed47 h25 aed46 j26 aed45 h26 aed44 j27 aed43 h27 i/o/z ipu emifa external data aed42 j28 aed41 c29 aed40 j29 aed39 d29 aed38 j25 aed37 f29 aed36 f26 aed35 g29 aed34 k28 aed33 k25 aed32 k27 aed31 aa27 aed30 ag29 aed29 ab29 aed28 ac27 aed27 ab28 aed26 ac26 aed25 ab27 aed24 ac25 aed23 ab26 aed22 ad28 device overview 30 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 2-3. terminal functions (continued) signal type (1) ipd/ipu (2) description name no. aed21 ad29 aed20 aj28 aed19 af29 aed18 ah28 aed17 ae29 aed16 ag28 aed15 af28 aed14 ah26 aed13 ae28 aed12 ae26 aed11 ad26 i/o/z ipu emifa external data aed10 af27 aed9 ag27 aed8 ad27 aed7 ae25 aed6 aj27 aed5 aj26 aed4 ae27 aed3 ag25 aed2 ah27 aed1 af25 aed0 ad25 ddr2 memory controller (32-bit) - control signals common to all types of memory ddr2 memory controller memory space enable. when the ddr2 memory dce0 e14 o/z controller is enabled, it always keeps this pin low. dba2 e15 o/z dba1 d15 o/z ddr2 memory controller bank address control dba0 c15 o/z ddr2clkout b14 o/z ddr2 memory controller output clock (clkin2 frequency 10) ddr2clkout a14 o/z negative ddr2 memory controller output clock (clkin2 frequency 10) dsdcas d13 o/z ddr2 memory controller sdram column-address strobe dsdras c13 o/z ddr2 memory controller sdram row-address strobe dsdwe b13 o/z ddr2 memory controller sdram write-enable dsdcke d14 o/z ddr2 memory controller sdram clock-enable (used for self-refresh mode). deodt1 a17 o/z on-die termination signals to external ddr2 sdram. these pins should not be connected to the ddr2 sdram. note: there are no on-die termination resistors implemented on the c6454 deodt0 e16 o/z dsp die. dsddqgate3 f21 i ddr2 memory controller data strobe gate [3:0] dsddqgate2 e21 o/z for hookup of these signals, please refer to the implementing ddr2 pcb layout on a TMS320C6454 hardware design application report (literature dsddqgate1 b9 i number spraaa9). dsddqgate0 a9 o/z dsddqm3 c23 o/z ddr2 memory controller byte-enable controls decoded from the low-order address bits. the number of address bits or dsddqm2 c20 o/z byte enables used depends on the width of external memory. dsddqm1 c8 o/z byte-write enables for most types of memory. dsddqm0 c11 o/z can be directly connected to sdram read and write mask signal (sdqm). submit documentation feedback device overview 31 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 2-3. terminal functions (continued) signal type (1) ipd/ipu (2) description name no. dsddqs3 e23 i/o/z dsddqs2 e20 i/o/z ddr2 memory controller data strobe [3:0] positive dsddqs1 e8 i/o/z dsddqs0 e11 i/o/z dsddqs3 d23 i/o/z ddr2 data strobe [3:0] negative dsddqs2 d20 i/o/z dsddqs1 d8 i/o/z note: these pins are used to meet ac timings. dsddqs0 d11 i/o/z ddr2 memory controller (32-bit) - address dea13 b15 dea12 a15 dea11 a16 dea10 b16 dea9 c16 dea8 d16 dea7 b17 o/z ddr2 memory controller external address dea6 c17 dea5 d17 dea4 e17 dea3 a18 dea2 b18 dea1 c18 dea0 d18 device overview 32 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 2-3. terminal functions (continued) signal type (1) ipd/ipu (2) description name no. ddr2 memory controller (32-bit) - data ded31 b25 ded30 a25 ded29 b24 ded28 a24 ded27 d22 ded26 c22 ded25 b22 ded24 a22 ded23 d21 ded22 c21 ded21 b21 ded20 a21 ded19 d19 ded18 c19 ded17 a19 ded16 b19 i/o/z ddr2 memory controller external data ded15 c7 ded14 d7 ded13 a7 ded12 b7 ded11 f9 ded10 e9 ded9 d9 ded8 c9 ded7 d10 ded6 c10 ded5 b10 ded4 a10 ded3 d12 ded2 c12 ded1 b12 ded0 a12 timer 1 toutl1 ag7 o/z ipd timer 1 output pin for lower 32-bit counter tinpl1 aj6 i ipd timer 1 input pin for lower 32-bit counter timer 0 toutl0 af8 o/z ipd timer 0 output pin for lower 32-bit counter tinpl0 ah6 i ipd timer 0 input pin for lower 32-bit counter inter-integrated circuit (i2c) scl ag26 i/o/z i2c clock. when the i2c module is used, use an external pullup resistor. sda af26 i/o/z i2c data. when i2c is used, ensure there is an external pullup resistor. submit documentation feedback device overview 33 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 2-3. terminal functions (continued) signal type (1) ipd/ipu (2) description name no. multichannel buffered serial port 1 and multichannel buffered serial port 0 (mcbsp1 and mcbsp0) mcbsp external clock source (as opposed to internal) ( i) clks aj4 i ipd [shared by mcbsp1 and mcbsp0] multichannel buffered serial port 1 (mcbsp1) clkr1/gp[0] af4 i/o/z ipd mcbsp1 receive clock ( i/o/z) or gp[0] ( i/o/z) [default] fsr1/gp[10] ae5 i/o/z ipd mcbsp1 receive frame sync ( i/o/z) or gp[10] ( i/o/z)[default] dr1/gp[8] ah5 i/o/z ipd mcbsp1 receive data ( i) or gp[8] ( i/o/z) [default] dx1/gp[9] ag5 i/o/z ipd mcbsp1 transmit data ( o/z) or gp[9] ( i/o/z) [default] fsx1/gp[11] ag4 i/o/z ipd mcbsp1 transmit frame sync ( i/o/z) or gp[11] ( i/o/z) [default] clkx1/gp[3] af5 i/o/z ipd mcbsp1 transmit clock ( i/o/z) or gp[3] ( i/o/z) [default] multichannel buffered serial port 0 (mcbsp0) clkr0 ag1 i/o/z ipu mcbsp0 receive clock ( i/o/z) fsr0 ah3 i/o/z ipd mcbsp0 receive frame sync ( i/o/z) dr0 aj5 i ipd mcbsp0 receive data ( i) dx0 af6 i/o/z ipd mcbsp0 transmit data ( o/z) fsx0 aj3 i/o/z ipd mcbsp0 transmit frame sync ( i/o/z) clkx0 ag6 i/o/z ipu mcbsp0 transmit clock ( i/o/z) management data input/output (mdio) for mii/rmii/gmii mdclk m5 i/o/z ipd mdio serial clock (mdclk) for mii/rmii/rgmii mode ( o) mdio n3 i/o/z ipu mdio serial data (mdio) for mii/rmii/rgmii mode ( i/o) management data input/output (mdio) for rgmii rgmdclk b4 o/z mdio serial clock for rgmii mode (rgmdclk) ( o) rgmdio a4 i/o/z mdio serial data for rgmii mode (rgmdio) ( i/o) ethernet mac (emac) [mii/rmii/gmii] there are two configuration pins ? the mac_sel[1:0] (aea[10:9] pins) that select one of the four interface modes (mii, rmii, gmii, or rgmii) for the emac/mdio interface. for more detailed information on the emac configuration pins, see section 3 , device configuration. this pin is emac receive clock (mrclk) for mii [default] or gmii. mrclk h1 i macsel[1:0] dependent. this pin is emac carrier sense (mcrs) ( i) for mii [default] or gmii, or emac mcrs/rmcrsdv j4 i/o/z carrier sense/receive data valid (rmcrsdv) ( i) for rmii. macsel[1:0] dependent. this pin is emac receive error (mrxir) ( i) for mii [default], rmii, or gmii. mrxer/rmrxer h4 i macsel[1:0] dependent. this pin is emac mii [default] or gmii receive data valid (mrxdv) ( i). mrxdv h5 i macsel[1:0] dependent. mrxd7 m2 mrxd6 h2 mrxd5 l2 emac receive data bus for mii [default], rmii, or gmii mrxd4 l1 i these pins function as emac receive data pins for mii [default], rmii, or gmii mrxd3 j3 (mrxd[x:0]) ( i). macsel[1:0] dependent. mrxd2 j1 mrxd1/rmrxd1 h3 mrxd0/rmrxd0 j2 gmtclk k5 o/z this pin is emac gmii transmit clock (gmtclk) ( o). macsel[1:0] dependent. this pin is either emac mii [default] or gmii transmit clock (mtclk) ( i) or the emac rmii reference clock (rmrefclk) ( i). the emac function is controlled mtclk/rmrefclk n4 i by the macsel[1:0] (aea[10:9] pins). for more detailed information, see section 3 , device configuration. device overview 34 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 2-3. terminal functions (continued) signal type (1) ipd/ipu (2) description name no. this pin is the emac collision sense (mcdl) ( i) for mii [default] or gmii. mcol k3 i/o/z macsel[1:0] dependent. this pin is either the emac transmit enable (mtxen) ( o) for mii [default], mtxen/rmtxen j5 i/o/z rmii, or gmii. macsel[1:0] dependent. mtxd7 n5 mtxd6 m3 mtxd5 l5 emac transmit data bus for mii [default], rmii, or gmii. mtxd4 l3 o/z these pins function as emac transmit data pins (mtxd[x:0]) ( o) for mii, rmii, mtxd3 k4 or gmii. macsel[1:0] dependent. mtxd2 m4 mtxd1/rmtxd1 l4 mtxd0/rmtxd0 m1 ethernet mac (emac) [rgmii] there are two configuration pins ? the mac_sel[1:0] (aea[10:9] pins) that select one of the four interface modes (mii, rmii, gmii, or rgmii) for the emac/mdio interface. for more detailed information on the emac configuration pins, see section 3 , device configuration. rgmii reference clock ( o). this 125-mhz reference clock is provided as a convenience. it can be used as a clock source to a phy, so that the phy may rgrefclk c4 o/z generate rxc clock to communicate with the emac. this clock is stopped while the device is in reset. this pin is available only when rgmii mode is selected ( macsel[1:0] =11). rgmii transmit clock ( o). this pin is available only when rgmii mode is rgtxc d4 o/z selected (macsel[1:0] =11). rgtxd3 a2 rgtxd2 c3 rgmii transmit data [3:0] ( o). this pin is available only when rgmii mode is o/z selected (macsel[1:0] =11). rgtxd1 b3 rgtxd0 a3 rgmii transmit enable ( o). this pin is available only when rgmii mode is rgtxctl d3 o/z selected (macsel[1:0] =11). rgmii receive clock ( i). this pin is available only when rgmii mode is selected rgrxc e3 i (macsel[1:0] =11). rgrxd3 c1 i rgrxd2 e4 i rgmii receive data [3:0] ( i). this pin is available only when rgmii mode is selected (macsel[1:0] =11). rgrxd1 e2 i rgrxd0 e1 i rgmii receive control ( i). this pin is available only when rgmii mode is rgrxctl c2 i selected (macsel[1:0] =11). reserved for test rsv02 v5 rsv03 w3 reserved. these pins must be connected directly to core supply (cv dd ) for proper device operation. rsv04 n11 rsv05 p11 rsv07 g4 i reserved. this pin must be connected directly to 1.5-/1.8-v i/o supply (dv dd15 ) for proper device operation. note: if the emac rgmii is not used, these pins can be connected directly to rsv09 d26 i ground (v ss ) . reserved. this pin must be connected to ground (v ss ) via a 200- w resistor for proper device operation. note: if the ddr2 memory controller is not used, the v refsstl , rsv11, and rsv12 pins can be connected directly to ground (v ss ) to save power. rsv11 d24 however, connecting these pins directly to ground will prevent boundary-scan from functioning on the ddr2 memory controller pins. to preserve boundary-scan functionality on the ddr2 memory controller pins, see section 7.3.4 . submit documentation feedback device overview 35 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 2-3. terminal functions (continued) signal type (1) ipd/ipu (2) description name no. reserved. this pin must be connected to the 1.8-v i/o supply (dv dd18 ) via a 200- w resistor for proper device operation. note: if the ddr2 memory controller is not used, the v refsstl , rsv11, and rsv12 pins can be connected directly to ground (v ss ) to save power. rsv12 c24 however, connecting these pins directly to ground will prevent boundary-scan from functioning on the ddr2 memory controller pins. to preserve boundary-scan functionality on the ddr2 memory controller pins, see section 7.3.4 . reserved. this pin must be connected to ground (v ss ) via a 200- w resistor for proper device operation. note: if the rgmii mode of the emac is not used, the dv dd15 , v refhstl , rsv13 f2 rsv13, and rsv14 pins can be connected to directly ground (v ss ) to save power. however, connecting these pins directly to ground will prevent boundary-scan from functioning on the rgmii pins of the emac. to preserve boundary-scan functionality on the rgmii pins, see section 7.3.4 . reserved. this pin must be connected to the 1.5/1.8-v i/o supply (dv dd15 ) via a 200- w resistor for proper device operation. note: if the rgmii mode of the emac is not used, the dv dd15 , v refhstl , rsv14 f1 rsv13, and rsv14 pins can be connected to directly ground (v ss ) to save power. however, connecting these pins directly to ground will prevent boundary-scan from functioning on the rgmii pins of the emac. to preserve boundary-scan functionality on the rgmii pins, see section 7.3.4 . reserved. this pin must be connected via a 39- w resistor directly to ground rsv15 t1 (v ss ) for proper device operation. the resistor used should have a minimal rating of 1/10 w. reserved. this pin must be connected via a 20- w resistor directly to 3.3-v i/o rsv16 t2 supply (dv dd33 ) for proper device operation. the resistor used should have a minimal rating of 1/10 w. device overview 36 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 2-3. terminal functions (continued) signal type (1) ipd/ipu (2) description name no. rsv17 ae21 a rsv18 e13 a rsv19 f18 a rsv20 u29 a rsv21 a6 a rsv22 b26 o rsv23 c26 o rsv24 b6 o rsv25 c6 o rsv26 aj11 a rsv27 ah11 a rsv36 ad11 i/o/z ipu rsv37 ad9 i/o/z ipu rsv38 ag10 i/o/z ipu rsv39 ag11 i/o/z ipu rsv40 aj12 i/o/z ipu rsv41 w28 o/z ipu rsv42 y26 o/z ipu rsv43 y25 o/z ipu reserved. (leave unconnected, do not connect to power or ground.) rsv44 y27 o/z rsv45 af15 i rsv46 ag15 i rsv47 af17 o/z rsv48 ag18 o/z rsv49 ag22 o/z rsv50 af23 o/z rsv51 af18 o/z rsv52 ag19 o/z rsv53 ag21 o/z rsv54 af22 o/z rsv55 ah18 i rsv56 aj18 i rsv57 aj22 i rsv58 ah22 i rsv59 ah17 i rsv60 aj19 i rsv61 aj21 i rsv62 ah23 i rsv28 n7 a rsv29 n6 a reserved. these pins must be connected directly to v ss for proper device operation. rsv30 p23 a rsv31 p24 a reserved. this pin must be connected to the 1.8-v i/o supply (dv dd18 ) via a rsv32 d25 1-k w resistor for proper device operation. reserved. this pin must be connected directly to ground for proper device rsv33 c25 operation. submit documentation feedback device overview 37 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 2-3. terminal functions (continued) signal type (1) ipd/ipu (2) description name no. reserved. this pin must be connected to the 1.8-v i/o supply (dv dd18 ) via a rsv34 e6 1-k w resistor for proper device operation. reserved. this pin must be connected directly to ground for proper device rsv35 d6 operation. rsv63 ad20 i rsv64 ac15 i rsv65 ac17 i rsv66 ad16 i rsv67 u16 i rsv68 v15 i rsv69 v17 i rsv70 w16 i reserved. these pins must be connected directly to v ss for proper device operation. rsv71 w18 i rsv72 ae17 i rsv73 ae19 i rsv74 ae23 i rsv75 af20 i rsv76 ah20 i rsv77 aj17 i rsv78 aj23 i supply voltage monitor pins die-side 1.2-v core supply (cv dd ) voltage monitor pin. the monitor pins indicate the voltage on the die and, therefore, provide the best probe point for cv ddmon n1 voltage monitoring purposes. for more information regarding the use of this and other voltage monitoring pins. if the cv ddmon pin is not used, it should be connected directly to the 1.2-v core supply (cv dd ). die-side 3.3-v i/o supply (dv dd33 ) voltage monitor pin. the monitor pins indicate the voltage on the die and, therefore, provide the best probe point for dv dd33mon l6 voltage monitoring purposes. for more information regarding the use of this and other voltage monitoring pins. if the dv dd33mon pin is not used, it should be connected directly to the 3.3-v i/o supply (dv dd33 ). die-side 1.5-/1.8-v i/o supply (dv dd15 ) voltage monitor pin. the monitor pins indicate the voltage on the die and, therefore, provide the best probe point for voltage monitoring purposes. for more information regarding the use of this and other voltage monitoring pins. if the dv dd15mon pin is not used, it should be connected directly to the 1.5-/1.8-v i/o supply (dv dd15 ). dv dd15mon f3 i note: if the rgmii mode of the emac is not used, the dv dd15 , dv dd15mon , v refhstl , rsv13, and rsv14 pins can be connected directly to ground (v ss ) to save power. however, connecting these pins directly to ground will prevent boundary-scan from functioning on the rgmii pins of the emac. to preserve boundary-scan functionality on the rgmii pins, see section 7.3.4 . die-side 1.8-v i/o supply (dv dd18 ) voltage monitor pin. the monitor pins indicate the voltage on the die and, therefore, provide the best probe point for dv dd18mon a26 voltage monitoring purposes. for more information regarding the use of this and other voltage monitoring pins. if the dv dd18mon pin is not used, it should be connected directly to the 1.8-v i/o supply (dv dd18 ). supply voltage pins (dv dd18 /2)-v reference for sstl buffer (ddr2 memory controller). this input voltage can be generated directly from dv dd18 using two 1-k w resistors to form a resistor divider circuit. note: the ddr2 memory controller is not used, the v refsstl , rsv11, and v refsstl c14 a rsv12 pins can be connected directly to ground (v ss ) to save power. however, connecting these pins directly to ground will prevent boundary-scan from functioning on the ddr2 memory controller pins. to preserve boundary-scan functionality on the ddr2 memory controller pins, see section 7.3.4 . device overview 38 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 2-3. terminal functions (continued) signal type (1) ipd/ipu (2) description name no. (dv dd15 /2)-v reference for hstl buffer (emac rgmii). v refhstl can be generated directly from dv dd15 using two 1-k w resistors to form a resistor divider circuit. note: if the rgmii mode of the emac is not used, the dv dd15 , v refhstl , v refhstl b2 a rsv13, and rsv14 pins can be connected to directly ground (v ss ) to save power. however, connecting these pins directly to ground will prevent boundary-scan from functioning on the rgmii pins of the emac. to preserve boundary-scan functionality on the rgmii pins, see section 7.3.4 . av dll1 a13 a 1.8-v i/o supply voltage. av dll2 e18 a1 b5 1.8-v or 1.5-v i/o supply voltage for the rgmii function of the emac. note: if the rgmii mode of the emac is not used, the dv dd15 , v refhstl , d2 rsv13, and rsv14 pins can be connected to directly ground (v ss ) to save dv dd15 d5 s power. however, connecting these pins directly to ground will prevent f5 boundary-scan from functioning on the rgmii pins of the emac. to preserve boundary-scan functionality on the rgmii pins, see section 7.3.4 . g6 h7 b8 b11 b20 b23 e10 e12 e22 e24 f7 f11 f13 f15 dv dd18 s 1.8-v i/o supply voltage (ddr2 memory controller) f17 f19 f23 g8 g10 g12 g14 g16 g18 g20 g22 g24 submit documentation feedback device overview 39 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 2-3. terminal functions (continued) signal type (1) ipd/ipu (2) description name no. a29 e26 e28 g2 h23 h28 j6 j24 k1 k7 k23 l24 m7 m23 m28 n24 p6 p28 r1 r6 r23 dv dd33 t7 s 3.3-v i/o supply voltage t24 u23 v1 v7 v24 w23 y7 y24 aa1 aa6 aa23 ab7 ab24 ac6 ac9 ac11 ac13 ac19 ac21 ac23 ac29 device overview 40 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 2-3. terminal functions (continued) signal type (1) ipd/ipu (2) description name no. ad5 ad7 ad14 ad18 ad22 ad24 ae6 ae8 ae15 af1 af16 dv dd33 af24 s 3.3-v i/o supply voltage ag12 ag17 ag23 ah14 ah16 ah24 aj1 aj7 aj15 aj25 aj29 l12 l14 l16 l18 m11 m13 m15 m17 m19 n12 cv dd s 1.2-v core supply voltage n14 n16 n18 p13 p15 p17 p19 r12 r14 r16 submit documentation feedback device overview 41 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 2-3. terminal functions (continued) signal type (1) ipd/ipu (2) description name no. r18 t11 t13 t15 t17 t19 u12 cv dd s 1.2-v core supply voltage u14 u18 v11 v13 v19 w12 w14 ground pins a8 a11 a20 a23 b1 b29 c5 d1 e5 e7 v ss gnd ground pins e19 e25 e29 f4 f6 f8 f10 f12 f14 f16 device overview 42 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 2-3. terminal functions (continued) signal type (1) ipd/ipu (2) description name no. f20 f22 f24 g1 g5 g7 g9 g11 g13 g15 g17 g19 g21 g23 h6 h24 v ss gnd ground pins h29 j7 j23 k2 k6 k24 l7 l11 l13 l15 l17 l19 l23 m6 m12 m14 submit documentation feedback device overview 43 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 2-3. terminal functions (continued) signal type (1) ipd/ipu (2) description name no. m16 m18 m24 m26 m29 n2 n13 n15 n17 n19 n23 p7 p12 p14 p16 p18 p29 v ss gnd ground pins r2 r7 r11 r13 r15 r17 r19 r24 t6 t12 t14 t16 t18 t23 u7 u11 u13 device overview 44 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 2-3. terminal functions (continued) signal type (1) ipd/ipu (2) description name no. u15 u17 u19 u24 v2 v6 v12 v14 v16 v18 v23 w7 w11 w13 w15 w17 v ss gnd ground pins w19 w24 y6 y23 aa2 aa7 aa24 ab6 ab23 ac7 ac8 ac10 ac12 ac14 ac16 ac18 submit documentation feedback device overview 45 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 2-3. terminal functions (continued) signal type (1) ipd/ipu (2) description name no. ac20 ac22 ac24 ac28 ad6 ad13 ad15 ad17 ad19 ad21 ad23 ae4 ae7 ae16 ae18 ae20 ae22 ae24 v ss gnd ground pins af2 af19 af21 ag13 ag16 ag20 ag24 ah1 ah15 ah19 ah21 ah25 ah29 aj8 aj14 aj16 aj20 aj24 device overview 46 submit documentation feedback www.ti.com product preview
2.8 development 2.8.1 development support 2.8.2 device support TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 in case the customer would like to develop their own features and software on the c6454 device, ti offers an extensive line of development tools for the tms320c6000? dsp platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. the tool's support documentation is electronically available within the code composer studio? integrated development environment (ide). the following products support development of c6000? dsp-based applications: software development tools: code composer studio? integrated development environment (ide): including editor c/c++/assembly code generation, and debug plus additional development tools scalable, real-time foundation software (dsp/bios?), which provides the basic run-time target software needed to support any dsp application. hardware development tools: extended development system (xds?) emulator (supports c6000? dsp multiprocessor system debug) evm (evaluation module) 2.8.2.1 device and development-support tool nomenclature to designate the stages in the product development cycle, ti assigns prefixes to the part numbers of all dsp devices and support tools. each dsp commercial family member has one of three prefixes: tmx, tmp, or tms (e.g., tmx320c6454ztz). texas instruments recommends two of three possible prefix designators for its support tools: tmdx and tmds. these prefixes represent evolutionary stages of product development from engineering prototypes (tmx/tmdx) through fully qualified production devices/tools (tms/tmds). device development evolutionary flow: tmx experimental device that is not necessarily representative of the final device's electrical specifications tmp final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification tms fully qualified production device support tool development evolutionary flow: tmdx development-support product that has not yet completed texas instruments internal qualification testing. tmds fully qualified development-support product tmx and tmp devices and tmdx development-support tools are shipped with against the following disclaimer: "developmental product is intended for internal evaluation purposes." tms devices and tmds development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. ti's standard warranty applies. predictions show that prototype devices (tmx or tmp) have a greater failure rate than the standard production devices. texas instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. only qualified production devices are to be used. submit documentation feedback device overview 47 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 ti device nomenclature also includes a suffix with the device family name. this suffix indicates the package type (for example, ztz), the temperature range (for example, blank is the default commercial temperature range), and the device speed range, in megahertz (for example, blank is 1000 mhz [1 ghz]). figure 2-12 provides a legend for reading the complete device name for any tms320c64x+? dsp generation member. for device part numbers and further ordering information for TMS320C6454 in the ztz/gtz package type, see the ti website ( www.ti.com ) or contact your ti sales representative. figure 2-12. tms320c64x+? dsp device nomenclature (including the TMS320C6454 dsp) 2.8.2.2 documentation support the following documents describe the TMS320C6454 fixed-point digital signal processor. copies of these documents are available on the internet at www.ti.com . tip: enter the literature number in the search box provided at www.ti.com. the current documentation that describes the TMS320C6454, related peripherals, and other technical collateral, is available in the c6000 dsp product folder at: www.ti.com/c6000 . spru732 tms320c64x/c64x+ dsp cpu and instruction set reference guide. describes the cpu architecture, pipeline, instruction set, and interrupts for the tms320c64x and tms320c64x+ digital signal processors (dsps) of the tms320c6000 dsp family. the c64x/c64x+ dsp generation comprises fixed-point devices in the c6000 dsp platform. the c64x+ dsp is an enhancement of the c64x dsp with added functionality and an expanded instruction set. spru862 tms320c64x+ dsp cache user's guide. explains the fundamentals of memory caches and describes how the two-level cache-based internal memory architecture in the tms320c64x+ digital signal processor (dsp) of the tms320c6000 dsp family can be efficiently used in dsp applications. shows how to maintain coherence with external memory, how to use dma to reduce memory latencies, and how to optimize your code to improve cache efficiency. the internal memory architecture in the c64x+ dsp is organized in a two-level hierarchy consisting of a dedicated program cache (l1p) and a dedicated data cache (l1d) on the first level. accesses by the cpu to the these first level caches can complete without cpu pipeline stalls. if the data requested by the cpu is not contained in cache, it is fetched from the next lower memory level, l2 or external memory. spru871 tms320c64x+ dsp megamodule reference guide. describes the tms320c64x+ digital signal processor (dsp) megamodule. included is a discussion on the internal direct memory access (idma) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache. spraa84 tms320c64x to tms320c64x+ cpu migration guide. describes migrating from the texas instruments tms320c64x digital signal processor (dsp) to the tms320c64x+ dsp. the device overview 48 submit documentation feedback www.ti.com product preview c64x+ dsp:c6454 prefix tmx 320 c6454 ztz tmx = experimental devicetms = qualified device device f amily 320 = tms320 dsp family p ackage type (a) ztz = 697-pin plastic bga, with pb-free solder ballsgtz = 697-pin plastic bga, with pb-ed solder balls device a. bga = ball grid array device speed range 7 = 720 mhz8 = 850 mhz blank = 1 ghz ( ) tempera ture range blank = 0 c to +90 c (default commercial temperature) ( )
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 objective of this document is to indicate differences between the two cores. functionality in the devices that is identical is not included. spru889 high-speed dsp systems design reference guide. provides recommendations for meeting the many challenges of high-speed dsp system design. these recommendations include information about dsp audio, video, and communications systems for the c5000 and c6000 dsp platforms. spru970 tms320c645x dsp ddr2 memory controller user's guide. this document describes the ddr2 memory controller in the tms320c645x digital-signal processors (dsps). spru966 tms320c645x dsp enhanced dma (edma3) controller user's guide. this document describes the enhanced dma (edma3) controller on the tms320c645x device. spru975 tms320c645x dsp emac/mdio module user's guide. this document provides a functional description of the ethernet media access controller (emac) and physical layer (phy) device management data input/output (mdio) module integrated with the devices of the tms320c645x family. spru971 tms320c645x dsp external memory interface (emif) user's guide. this document describes the operation of the external memory interface (emif) in the digital signal processors (dsps) of the tms320c645x dsp family. spru724 tms320c645x dsp general-purpose input/output (gpio) user's guide. this document describes the general-purpose input/output (gpio) peripheral in the digital signal processors (dsps) of the tms320c645x dsp family. the gpio peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs. when configured as an input, you can detect the state of the input by reading the state of an internal register. when configured as an output, you can write to an internal register to control the state driven on the output pin. spru969 tms320c645x dsp host port interface (hpi) user's guide. this guide describes the host port interface (hpi) on the tms320c645x digital signal processors (dsps). the hpi enables an external host processor (host) to directly access dsp resources (including internal and external memory) using a 16-bit (hpi16) or 32-bit (hpi32) interface. spru974 tms320c645x dsp inter-integrated circuit (i2c) module user's guide. this document describes the inter-integrated circuit (i2c) module in the tms320c645x digital signal processor (dsp). the i2c provides an interface between the tms320c645x device and other devices compliant with philips semiconductors inter-ic bus (i2c-bus) specification version 2.1 and connected by way of an i2c-bus. this document assumes the reader is familiar with the i2c-bus specification. sprue60 tms320c645x dsp peripheral component interconnect (pci) user's guide. this document describes the peripheral component interconnect (pci) port in tms320c645x devices. see the pci specification revision 2.3 for details on the pci interface. sprue56 tms320c645x dsp software-programmable phase-locked loop (pll) controller user's guide. this document describes the operation of the software-programmable phase-locked loop (pll) controller in the tms320c645x digital signal processors (dsps). the pll controller offers flexibility and convenience by way of software-configurable multipliers and dividers to modify the input signal internally. the resulting clock outputs are passed to the tms320c645x dsp core, peripherals, and other modules inside the tms320c645x dsp. spru968 tms320c645x dsp 64-bit timer user's guide. this document provides an overview of the 64-bit timer in the tms320c645x dsp. the timer can be configured as a general-purpose 64-bit timer, dual general-purpose 32-bit timers, or a watchdog timer. when configured as a dual 32-bit timers, each half can operate in conjunction (chain mode) or independently (unchained mode) of each other. submit documentation feedback device overview 49 product preview www.ti.com
3 device configuration 3.1 device configuration at device reset TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 on the c6454 device, certain device configurations like boot mode, pin multiplexing, and endianess, are selected at device reset. the status of the peripherals (enabled/disabled) is determined after device reset. by default, the peripherals on the c6454 device are disabled and need to be enabled by software before being used. table 3-1 describes the c6454 device configuration pins. the logic level of the aea[19:0], aba[1:0], and pci_en pins is latched at reset to determine the device configuration. the logic level on the device configuration pins can be set by using external pullup/pulldown resistors or by using some control device (e.g., fpga/cpld) to intelligently drive these pins. when using a control device, care should be taken to ensure there is no contention on the lines when the device is out of reset. the device configuration pins are sampled during reset and are driven after the reset is removed. to avoid contention, the control device should only drive the emifa pins when resetstat is low. note if a configuration pin must be routed out from the device and 3-stated (not driven), the internal pullup/pulldown (ipu/ipd) resistor should not be relied upon; ti recommends the use of an external pullup/pulldown resistor. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.7 , pullup/pulldown resistors. table 3-1. c6454 device configuration pins (aea[19:0], aba[1:0], and pci_en) configuration ipd/ no. functional description pin ipu (1) boot mode selections (bootmode [3:0]). these pins select the boot mode for the device. 0000 no boot (default mode) 0001 host boot (hpi) 0010 reserved 0011 reserved [n25, 0100 emifa 8-bit rom boot l26, 0101 master i2c boot aea[19:16] ipd l25, 0110 slave i2c boot p26] 0111 host boot (pci) 1000 thru reserved 1111 if selected for boot, the corresponding peripheral is automatically enabled after device reset. for more detailed information on boot modes, see section 2.4 , boot sequence. cfggp[2:0] pins must be set to 000b during reset for proper operation of the pci boot mode. emifa input clock source select (aeclkin_sel). 0 aeclkin (default mode) aea15 p27 ipd 1 sysclk4 (cpu/x) clock rate. the sysclk4 clock rate is software selectable via the software pll1 controller. by default, sysclk4 is selected as cpu/8 clock rate. (1) ipd = internal pulldown, ipu = internal pullup. for most systems, a 1-k w resistor can be used to oppose the ipu/ipd. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.7 , pullup/pulldown resistors. device configuration 50 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 3-1. c6454 device configuration pins (aea[19:0], aba[1:0], and pci_en) (continued) configuration ipd/ no. functional description pin ipu (1) hpi peripheral bus width select (hpi_width). 0 hpi operates in hpi16 mode (default). hpi bus is 16 bits wide; hd[15:0] pins are used and the remaining hd[31:16] pins are reserved pins in the hi-z state. aea14 r25 ipd 1 hpi operates in hpi32 mode. hpi bus is 32 bits wide; hd[31:0] pins are used. applies only when hpi function of hpi/pci multiplexed pins is selected (pci_en pin = 0). device endian mode (lendian). aea13 r27 ipu 0 system operates in big endian mode. 1 system operates in little endian mode (default). for proper c6454 device operation, this pin must be externally pulled down with a 1-k w aea12 r28 ipd resistor at device reset. for proper c6454 device operation, this pin must be externally pulled down with a 1-k w aea11 t25 ipd resistor at device reset. emac interface selects (macsel[1:0]). these pins select the interface used by the emac/mdio peripheral. 00 10/100 emac/mdio with mii interface [default] [m25, 01 10/100 emac/mdio with rmii interface aea[10:9] ipd m27] 10 10/100/1000 emac/mdio with gmii interface 11 10/100/1000 emac/mdio with rgmii interface for more detailed information on the mac_sel[1:0] control pin selections, see table 3-3 . pci i2c eeprom auto-initialization (pci_eeai). pci auto-initialization via external i2c eeprom 0 pci auto-initialization through external i2c eeprom is disabled. the pci peripheral uses the specified pci default values (default). aea8 p25 ipd 1 pci auto-initialization through external i2c eeprom is enabled. the pci peripheral is configured through external i2c eeprom provided the pci peripheral pins are enabled (pci_en = 1). note: if the pci pin function is disabled (pci_en pin = 0), this pin must not be pulled up. aea7 n27 ipd for proper c6454 device operation, do not oppose the ipd on this pin. pci frequency selection (pci66). selects the operating frequency of the pci (either 33 mhz or 66 mhz). 0 pci operates at 33 mhz (default) aea6 u27 ipd 1 pci operates at 66 mhz note: if the pci pin function is disabled (pci_en pin = 0), this pin must not be pulled up. mcbsp1 pin function enable bit (mcbsp1_en). selects which function is enabled on the mcbsp1/gpio multiplexed pins. 0 gpio pin function enabled (default). aea5 u28 ipd this means all multiplexed mcbsp1/gpio pins function as gpio pins. 1 mcbsp1 pin function enabled. this means all multiplexed mcbsp1/gpio pins function as mcbsp1 pins. sysclkout enable bit (sysclkout_en). selects which function is enabled on the sysclk4/gp[1] muxed pin. aea4 t28 ipd 0 gp[1] pin function is enabled (default) 1 sysclk4 pin function is enabled for proper c6454 device operation, the aea3 pin must be pulled down to v ss using a 1-k w aea3 t27 ipd resistor. configuration general-purpose inputs (cfggp[2:0]) [t26, the value of these pins is latched to the device status register following device reset and is aea[2:0] u26, ipd used by the on-chip bootloader for some boot modes. for more information on the boot u25] modes, see section 2.4 , boot sequence. submit documentation feedback device configuration 51 product preview www.ti.com
3.2 peripheral configuration at device reset TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 3-1. c6454 device configuration pins (aea[19:0], aba[1:0], and pci_en) (continued) configuration ipd/ no. functional description pin ipu (1) pci pin function enable bit (pci_en). selects which function is enabled on the hpi/pci multiplexed pins. 0 hpi pin function enabled (default) pci_en y29 ipd this means all multiplexed hpi/pci pins function as hpi pins. 1 pci pin function enabled this means all multiplexed hpi/pci pins function as pci pins. ddr2 memory controller enable (ddr2_en). aba0 v26 ipd 0 ddr2 memory controller peripheral pins are disabled (default) 1 ddr2 memory controller peripheral pins are enabled emifa enable (emifa_en). aba1 v25 ipd 0 emifa peripheral pins are disabled (default) 1 emifa peripheral pins are enabled some c6454 peripherals share the same pins (internally multiplexed) and are mutually exclusive. therefore, not all peripherals may be used at the same time. the device configuration pins described in section 3.1 , device configuration at device reset, determine which function is enabled for the multiplexed pins. note that when the pin function of a peripheral is disabled at device reset, the peripheral is permanently disabled and cannot be enabled until its pin function is enabled and another device reset is executed. also, note that enabling the pin function of a peripheral does not enable the corresponding peripheral. all peripherals on the c6454 device are disabled by default, except when used for boot, and must be enabled through software before being used. other peripheral options like pci clock speed and emac/mdio interface mode can also be selected at device reset through the device configuration pins. the configuration selected is also fixed at device reset and cannot be changed until another device reset is executed with a different configuration selected. the multiply factor of the pll1 controller is not selected through the configuration pins. the pll1 multiply factor is set in software through the pll1 controller registers after device reset. the pll2 multiply factor is fixed. for more information, see section 7.7 , pll1 and pll1 controller, and section 7.8 , pll2 and pll2 controller. on the c6454 device, the pci peripheral pins are multiplexed with the hpi pins. the pci_en pin selects the function for the hpi/pci multiplexed pins. the pci66, pci_eeai, and hpi_width control other functions of the pci and hpi peripherals. table 3-2 describes the effect of the pci_en, pci66, pci_eeai, and hpi_width configuration pins. table 3-2. pci_en, pci66, pci_eeai, and hpi_width peripheral selection (hpi and pci) configuration pin setting (1) peripheral function selected pci66 pci_eeai hpi_width pci_en pin hpi data hpi data 32-bit pci pci aea6 pin aea8 pin aea14 pin [y29] lower upper (66-/33-mhz) auto-init [u27] [p25] (1) [r25] 0 0 0 0 enabled hi-z disabled n/a 0 0 0 1 enabled enabled disabled n/a enabled 1 1 1 x disabled (via external i2c enabled eeprom) (66 mhz) 1 1 0 x disabled disabled (1) pci_eeai is latched at reset as a configuration input. if pci_eeai is set as one, then default values are loaded from an external i2c eeprom. device configuration 52 submit documentation feedback www.ti.com product preview
3.3 peripheral selection after device reset TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 3-2. pci_en, pci66, pci_eeai, and hpi_width peripheral selection (hpi and pci) (continued) configuration pin setting (1) peripheral function selected pci66 pci_eeai hpi_width pci_en pin hpi data hpi data 32-bit pci pci aea6 pin aea8 pin aea14 pin [y29] lower upper (66-/33-mhz) auto-init [u27] [p25] (1) [r25] disabled 1 0 0 x disabled (default values) enabled enabled (33 mhz) 1 0 1 x disabled (via external i2c eeprom) the mac_sel[1:0] configuration pins (aea[10:9) control which interface is used by the emac/mdio. table 3-3 describes the effect of the macsel[1:0] configuration pins. table 3-3. mac_sel[1:0] peripheral selection (emac) mac_sel[1:0]/ emac/mdio aea[10:9] pins [m25, m27] peripheral function selected configuration pin setting 00b 10/100 emac/mdio with mii interface [default] 01b 10/100 emac/mdio with rmii interface 10b 10/100/1000 emac/mdio with gmii interface 11b 10/100/1000 emac/mdio with rgmii interface (1) (1) rgmii interface requires a 1.5-/1.8-v i/o supply. on the c6454 device, peripherals can be in one of several states. these states are listed in table 3-4 . table 3-4. peripheral states peripherals that can state description be in this state hpi pci peripheral pin function has been completely disabled through the device mcbsp1 static powerdown configuration pins. peripheral is held in reset and clock is turned off. emac/mdio emifa ddr2 memory controller i2c timer 0 timer 1 gpio peripheral is held in reset and clock is turned off. default state for all disabled emac/mdio peripherals not in static powerdown mode. mcbsp0 mcbsp1 hpi pci i2c timer 0 timer 1 gpio mdio emac/mdio enabled clock to the peripheral is turned on and the peripheral is taken out of reset. mcbsp0 mcbsp1 hpi pci emifa ddr2 memory controller not a user-programmable state. this is an intermediate state when all peripherals that can be in enable in progress transitioning from an disabled state to an enabled state. an enabled state. submit documentation feedback device configuration 53 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 following device reset, all peripherals that are not in the static powerdown state are in the disabled state by default. peripherals used for boot such as hpi and pci are enabled automatically following a device reset. peripherals are only allowed certain transitions between states (see figure 3-1 ). figure 3-1. peripheral transitions between states figure 3-2 shows the flow needed to change the state of a given peripheral on the c6454 device. figure 3-2. peripheral state change flow a 32-bit key (value = 0x0f0a 0b00) must be written to the peripheral lock register (perlock) in order to allow access to the percfg0 register. writes to the percfg1 register can be done directly without going through the perlock register. note the instructions that write to the perlock and percfg0 registers must be in the same fetch packet if code is being executed from external memory. if the instructions are in different fetch packets, fetching the second instruction from external memory may stall the instruction long enough such that percfg0 register will be locked before the instruction is executed. 54 device configuration submit documentation feedback www.ti.com product preview reset static powerdown disabled enable in progress enabled unlock the percfg0 register by using the perlock register . w rite to the percfg0 register within 16 sysclk3 clock cycles to change the state of the peripherals. poll the perst a t registers to verify state change.
3.4 device state control registers TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the c6454 device has a set of registers that are used to control the status of its peripherals. these registers are shown in table 3-5 and described in the next sections. note the device state control registers can only be accessed using the cpu or the emulator. table 3-5. device state control registers hex address range acronym register name 02ac 0000 - reserved 02ac 0004 perlock peripheral lock register 02ac 0008 percfg0 peripheral configuration register 0 02ac 000c - reserved 02ac 0010 - reserved 02ac 0014 perstat0 peripheral status register 0 02ac 0018 perstat1 peripheral status register 1 02ac 001c - 02ac 001f - reserved 02ac 0020 emaccfg emac configuration register 02ac 0024 - 02ac 002b - reserved 02ac 002c percfg1 peripheral configuration register 1 02ac 0030 - 02ac 0053 - reserved 02ac 0054 emubufpd emulator buffer powerdown register 02ac 0058 - reserved submit documentation feedback device configuration 55 product preview www.ti.com
3.4.1 peripheral lock register description TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 when written with correct 32-bit key (0x0f0a0b00), the peripheral lock register (perlock) allows one write to the percfg0 register within 16 sysclk3 cycles. note the instructions that write to the perlock and percfg0 registers must be in the same fetch packet if code is being executed from external memory. if the instructions are in different fetch packets, fetching the second instruction from external memory may stall the instruction long enough such that percfg0 register will be locked before the instruction is executed. 31 0 lockval r/w-f0f0 f0f0 legend: r/w = read/write; - n = value after reset figure 3-3. peripheral lock register (perlock) - 0x02ac 0004 table 3-6. peripheral lock register (perlock) field descriptions bit field value description 31:0 lockval when programmed with 0x0f0a 0b00 allows one write to the percfg0 register within 16 sysclk3 clock cycles. device configuration 56 submit documentation feedback www.ti.com product preview
3.4.2 peripheral configuration register 0 description TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the peripheral configuration register (percfg0) is used to change the state of the peripherals. one write is allowed to this register within 16 sysclk3 cycles after the correct key is written to the perlock register. note the instructions that write to the perlock and percfg0 registers must be in the same fetch packet if code is being executed from external memory. if the instructions are in different fetch packets, fetching the second instruction from external memory may stall the instruction long enough such that percfg0 register will be locked before the instruction is executed. 31 24 reserved r/w-0 23 21 20 19 18 17 16 reserved pcictl reserved hpictl reserved mcbsp1ctl r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 15 14 13 12 11 10 9 8 reserved mcbsp0ctl reserved i2cctl reserved gpioctl reserved timer0ctl r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 7 6 5 4 3 0 reserved timer1ctl reserved emacctl reserved r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 legend: r/w = read/write; - n = value after reset figure 3-4. peripheral configuration register 0 (percfg0) - 0x02ac 0008 table 3-7. peripheral configuration register 0 (percfg0) field descriptions bit field value description 31:21 reserved reserved. 20 pcictl mode control for pci. this bit defaults to 1 when host boot is used (bootmode[3:0] = 0111b). 0 set pci to disabled mode 1 set pci to enabled mode 19 reserved reserved. 18 hpictl mode control for hpi. this bit defaults to 1 when host boot is used (bootmode[3:0] = 0001b). 0 set hpi to disabled mode 1 set hpi to enabled mode 17 reserved 1 reserved. 16 mcbsp1ctl mode control for mcbsp1 0 set mcbsp1 to disabled mode 1 set mcbsp1 to enabled mode 15 reserved reserved. 14 mcbsp0ctl mode control for mcbsp0 0 set mcbsp0 to disabled mode 1 set mcbsp0 to enabled mode 13 reserved reserved. submit documentation feedback device configuration 57 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 3-7. peripheral configuration register 0 (percfg0) field descriptions (continued) bit field value description 12 i2cctl mode control for i2c 0 set i2c to disabled mode 1 set i2c to enabled mode 11 reserved reserved. 10 gpioctl mode control for gpio 0 set gpio to disabled mode 1 set gpio to enabled mode 9 reserved reserved. 8 timer0ctl mode control for timer 0 0 set timer 0 to disabled mode 1 set timer 0 to enabled mode 7 reserved reserved. 6 timer1ctl mode control for timer 1 0 set timer 1 to disabled mode 1 set timer 1 to enabled mode 5 reserved reserved. 4 emacctl mode control for emac/mdio 0 set emac/mdio to disabled mode 1 set emac/mdio to enabled mode 3:0 reserved reserved. device configuration 58 submit documentation feedback www.ti.com product preview
3.4.3 peripheral configuration register 1 description TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the peripheral configuration register (percfg1) is used to enable the emifa and ddr2 memory controller. emifa and the ddr2 memory controller do not have corresponding status bits in the peripheral status registers. the emifa and ddr2 memory controller peripherals can be used within 16 sysclk3 cycles after emifactl and ddr2ctl are set to 1. once emifactl and ddr2ctl are set to 1, they cannot be set to 0. note that if the ddr2 memory controller and emifa are disabled at reset through the device configuration pins (ddr2.en[aba0] and emifa[aba1]), they cannot be enabled through the percfg1 register. 31 8 reserved r-0x00 7 2 1 0 reserved ddr2ctl emifactl r-0x00 r/w-0 r/w-0 legend: r/w = read/write; r = read only; - n = value after reset figure 3-5. peripheral configuration register 1 (percfg1) - 0x02ac 002c table 3-8. peripheral configuration register 1 (percfg1) field descriptions bit field value description 31:2 reserved reserved. 1 ddr2ctl mode control for ddr2 memory controller. once this bit is set to 1, it cannot be changed to 0. 0 set ddr2 to disabled 1 set ddr2 to enabled 0 emifactl mode control for emifa. once this bit is set to 1, it cannot be changed to 0. this bit defaults to 1 if emifa 8-bit rom boot is used (bootmode[3:0] = 0100b). 0 set emifa to disabled 1 set emifa to enabled submit documentation feedback device configuration 59 product preview www.ti.com
3.4.4 peripheral status registers description TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the peripheral status registers (perstat0 and perstat1) show the status of the c6454 peripherals. 31 30 29 27 26 24 reserved hpistat mcbsp1stat r-0 r-0 r-0 23 21 20 18 17 16 mcbsp0stat i2cstat gpiostat r-0 r-0 r-0 15 14 12 11 9 8 gpiostat timer1stat timer0stat emacstat r-0 r-0 r-0 r-0 7 6 5 0 emacstat reserved r-0 r-0 legend: r = read only; - n = value after reset figure 3-6. peripheral status register 0 (perstat0) - 0x02ac 0014 table 3-9. peripheral status register 0 (perstat0) field descriptions bit field value description 31:30 reserved reserved. 29:27 hpistat hpi status 000 hpi is in the disabled state 001 hpi is in the enabled state 011 hpi is in the static powerdown state 101 hpi is in the enable in progress state others reserved 26:24 mcbsp1stat mcbsp1 status 000 mcbsp1 is in the disabled state 001 mcbsp1 is in the enabled state 011 mcbsp1 is in the static powerdown state 101 mcbsp1 is in the enable in progress state others reserved 23:21 mcbsp0stat mcbsp0 status 000 mcbsp0 is in the disabled state 001 mcbsp0 is in the enabled state 011 mcbsp0 is in the static powerdown state 101 mcbsp0 is in the enable in progress state others reserved 20:18 i2cstat i2c status 000 i2c is in the disabled state 001 i2c is in the enabled state 011 i2c is in the static powerdown state 101 i2c is in the enable in progress state others reserved device configuration 60 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 3-9. peripheral status register 0 (perstat0) field descriptions (continued) bit field value description 17:15 gpiostat gpio status 000 gpio is in the disabled state 001 gpio is in the enabled state 011 gpio is in the static powerdown state 101 gpio is in the enable in progress state others reserved 14:12 timer1stat timer1 status 000 timer1 is in the disabled state 001 timer1 is in the enabled state 011 timer1 is in the static powerdown state 101 timer1 is in the enable in progress state others reserved 11:9 timer0stat timer0 status 000 timer0 is in the disabled state 001 timer0 is in the enabled state 011 timer0 is in the static powerdown state 101 timer0 is in the enable in progress state others reserved 8:6 emacstat emac/mdio status 000 emac/mdio is in the disabled state 001 emac/mdio is in the enabled state 011 emac/mdio is in the static powerdown state 101 emac/mdio is in the enable in progress state others reserved 5:0 reserved reserved submit documentation feedback device configuration 61 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 31 16 reserved r-0 15 3 2 0 reserved pcistat r-0 r-0 legend: r = read only; - n = value after reset figure 3-7. peripheral status register 1 (perstat1) - 0x02ac 0018 table 3-10. peripheral status register 1 (perstat1) field descriptions bit field value description 31:3 reserved reserved 2:0 pcistat pci status 000 pci is in the disabled state 001 pci is in the enabled state 011 pci is in the static powerdown state 101 pci is in the enable in progress state others reserved device configuration 62 submit documentation feedback www.ti.com product preview
3.4.5 emac configuration register (emaccfg) description TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the emac configuration register (emaccfg) is used to assert and deassert the reset of the reduced media independent interface (rmii) logic of the emac. for more details on how to use this register, see section 7.14 , ethernet mac (emac). 31 24 reserved r/w-0 23 19 18 17 16 reserved rmii_rst reserved r/w-0001b r/w-1 r/w-0 15 0 reserved r/w-0 legend: r/w = read/write; r = read only; - n = value after reset figure 3-8. emac configuration register (emaccfg) - 0x02ac 0020 table 3-11. emac configuration register (emaccfg) field descriptions bit field value description 31:19 reserved reserved. writes to this register must keep the default values of these bits. 18 rmii_rst rmii reset bit. this bit is used to reset the rmii logic of the emac. 0 rmii logic reset is released. 1 rmii logic reset is asserted. 17:0 reserved reserved. writes to this register must keep this bit as 0. submit documentation feedback device configuration 63 product preview www.ti.com
3.4.6 emulator buffer powerdown register (emubufpd) description TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the emulator buffer powerdown register (emubufpd) is used to control the state of the pin buffers of emulator pins emu[18:2]. these buffers can be powered down if the device trace feature is not needed. 31 8 reserved r-0 7 1 0 reserved emuctl r-0 r/w-0 legend: r/w = read/write; r = read only; - n = value after reset figure 3-9. emulator buffer powerdown register (emubufpd) - 0x02ac 0054 table 3-12. emulator buffer powerdown register (emubufpd) field descriptions bit field value description 31:1 reserved reserved 0 emuctl buffer powerdown for emu[18:2] pins 0 power-up buffers 1 power-down buffers device configuration 64 submit documentation feedback www.ti.com product preview
3.5 device status register description TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the device status register depicts the device configuration selected upon device reset. once set, these bits will remain set until a device reset. for the actual register bit names and their associated bit field descriptions, see figure 3-10 and table 3-13 . note that enabling or disabling peripherals through the peripheral configuration registers (percfg0 and percfg1) does not affect the devstat register. to determine the status of peripherals following writes to the percfg0 and percfg1 registers, read the peripherals status registers (perstat0 and perstat1). 31 24 reserved r-0000 0000 23 22 21 20 19 18 17 16 reserved emifa_en ddr2_en pci_en cfggp2 cfggp1 cfggp0 reserved r-0 r-x r-x r-x r-x r-x r-x r-1 15 14 13 12 11 10 9 8 sysclkout_ mcbsp1_en pci66 reserved pci_eeai mac_sel1 mac_sel0 reserved en r-x r-x r-x r-0 r-x r-x r-x r-1 7 6 5 4 3 2 1 0 reserved lendian hpi_width aeclkinsel bootmode3 bootmode2 bootmode1 bootmode0 r-0 r-x r-x r-x r-x r-x r-x r-x legend: r/w = read/write; r = read only; - x = value after reset figure 3-10. device status register (devstat) - 0x02a8 0000 table 3-13. device status register (devstat) field descriptions bit field value description 31:23 reserved reserved. read-only, writes have no effect. 22 emifa_en emifa enable (emifa_en) status bit shows the status of whether the emifa peripheral pins are enabled/disabled. 0 emifa peripheral pins are disabled (default) 1 emifa peripheral pins are enabled 21 ddr2_en ddr2 memory controller enable (ddr2_en) status bit shows the status of whether the ddr2 memory controller peripheral pins are enabled/disabled. 0 ddr2 memory controller peripheral pins are disabled (default) 1 ddr2 memory controller peripheral pins are enabled 20 pci_en pci enable (pci_en) status bit shows the status of which function is enabled on the hpi/pci multiplexed pins. 0 hpi pin functions are enabled (default) 1 pci pin functions are enabled 19:17 cfggp[2:0] used as general-purpose inputs for configuration purposes. these pins are latched at reset. these values can be used by s/w routines for boot operations. 16 reserved reserved. read-only, writes have no effect. 15 sysclkout_en sysclkout enable (sysclkout_en) status bit shows the status of which function is enabled on the sysclk4/gp[1] muxed pin. 0 gp[1] pin function of the sysclk4/gp[1] pin enabled (default) 1 sysclk4 pin function of the sysclk4/gp[1] pin enabled submit documentation feedback device configuration 65 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 3-13. device status register (devstat) field descriptions (continued) bit field value description 14 mcbsp1_en mcbsp1 enable (mcbsp1_en) status bit shows the status of which function is enabled on the mcbsp1/gpio muxed pins. 0 gpio pin functions enabled (default) 1 mcbsp1 pin functions enabled 13 pci66 pci frequency selection (pci66) status bit shows the pci operating frequency selected at reset. 0 pci operates at 33 mhz (default) 1 pci operates at 66 mhz 12 reserved reserved. read-only, writes have no effect. 11 pci_eeai pci i2c eeprom auto-initialization (pci_eeai) status bit shows whether the pci auto-initialization via external i2c eeprom is enabled/disabled. 0 pci auto-initialization through external i2c eeprom is disabled; the pci peripheral uses the specified pci default values (default). 1 pci auto-initialization through external i2c eeprom is enabled; the pci peripheral is configured through external i2c eeprom provided the pci peripheral pin is enabled (pci_en = 1). 10:9 macsel[1:0] emac interface select (macsel[1:0]) status bits shows which emac interface mode has been selected. 00 10/100 emac/mdio with mii interface (default) 01 10/100 emac/mdio with rmii interface 10 10/100/1000 emac/mdio with gmii interface 11 10/100/1000 emac/mdio with rgmii mode interface [rgmii interface requires a 1.8 v or 1.5 v i/o supply] 8:7 reserved reserved. read-only, writes have no effect. 6 lendian device endian mode (lendian) shows the status of whether the system is operating in big endian mode or little endian mode (default). 0 system is operating in big endian mode 1 system is operating in little endian mode (default) 5 hpi_width hpi bus width control bit. shows the status of whether the hpi bus operates in 32-bit mode or in 16-bit mode (default). 0 hpi operates in 16-bit mode. (default) 1 hpi operates in 32-bit mode 4 aeclkinsel emifa input clock select shows the status of what clock mode is enabled or disabled for emifa. 0 aeclkin (default mode) 1 sysclk4 (cpu/x) clock rate. the sysclk4 clock rate is software selectable via the pll1 controller. by default, sysclk4 is selected as cpu/8 clock rate. device configuration 66 submit documentation feedback www.ti.com product preview
3.6 jtag id (jtagid) register description 3.7 pullup/pulldown resistors TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 3-13. device status register (devstat) field descriptions (continued) bit field value description 3:0 bootmode[3:0] boot mode configuration bits shows the status of what device boot mode configuration is operational. bootmode[3:0] [ note: if selected for boot, the corresponding peripheral is automatically enabled after device reset.] 0000 no boot (default mode) 0001 host boot (hpi) 0010 reserved 0011 reserved 0100 emifa 8-bit rom boot 0101 master i2c boot 0110 slave i2c boot 0111 host boot (pci) 1000 reserved thru 1111 for more detailed information on the boot modes, see section 2.4 , boot sequence. the jtag id register is a read-only register that identifies to the customer the jtag/device id. for the c6454 device, the jtag id register resides at address location 0x02a8 0008. for the actual register bit names and their associated bit field descriptions, see figure 3-11 and table 3-14 . 31 28 27 12 11 1 0 variant part number manufacturer lsb (4-bit) (16-bit) (11-bit) r-n r-0000 0000 1000 1010b 0000 0010 111b r-1 legend: r = read only; - n = value after reset figure 3-11. jtag id (jtagid) register - 0x02a8 0008 table 3-14. jtag id (jtagid) register field descriptions bit field value description 31:28 variant variant (4-bit) value. the value of this field depends on the silicon revision being used. for more information, see the tms320c6455/54 digital signal processor silicon errata (literature number sprz234 ). note: the variant field may be invalid if no clkin1 signal is applied. 27:12 part number part number (16-bit) value. c6454 value: 0000 0000 1000 1010b. 11:1 manufacturer manufacturer (11-bit) value. c6454 value: 0000 0010 111b. 0 lsb lsb. this bit is read as a "1" for c6454. proper board design should ensure that input pins to the c6454 device always be at a valid logic level and not floating. this may be achieved via pullup/pulldown resistors. the c6454 device features internal pullup (ipu) and internal pulldown (ipd) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors. an external pullup/pulldown resistor needs to be used in the following situations: device configuration pins: if the pin is both routed out and 3-stated (not driven), an external pullup/pulldown resistor must be used, even if the ipu/ipd matches the desired value/state. submit documentation feedback device configuration 67 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 other input pins: if the ipu/ipd does not match the desired value/state, use an external pullup/pulldown resistor to pull the signal to the opposite rail. for the device configuration pins (listed in table 3-1 ), if they are both routed out and 3-stated (not driven), it is strongly recommended that an external pullup/pulldown resistor be implemented. although, internal pullup/pulldown resistors exist on these pins and they may match the desired configuration value, providing external connectivity can help ensure that valid logic levels are latched on these device configuration pins. in addition, applying external pullup/pulldown resistors on the device configuration pins adds convenience to the user in debugging and flexibility in switching operating modes. tips for choosing an external pullup/pulldown resistor: consider the total amount of current that may pass through the pullup or pulldown resistor. make sure to include the leakage currents of all the devices connected to the net, as well as any internal pullup or pulldown resistors. decide a target value for the net. for a pulldown resistor, this should be below the lowest v il level of all inputs connected to the net. for a pullup resistor, this should be above the highest v ih level of all inputs on the net. a reasonable choice would be to target the v ol or v oh levels for the logic family of the limiting device; which, by definition, have margin to the v il and v ih levels. select a pullup/pulldown resistor with the largest possible value; but, which can still ensure that the net will reach the target pulled value when maximum current from all devices on the net is flowing through the resistor. the current to be considered includes leakage current plus, any other internal and external pullup/pulldown resistors on the net. for bidirectional nets, there is an additional consideration which sets a lower limit on the resistance value of the external resistor. verify that the resistance is small enough that the weakest output buffer can drive the net to the opposite logic level (including margin). remember to include tolerances when selecting the resistor value. for pullup resistors, also remember to include tolerances on the dv dd rail. for most systems, a 1-k w resistor can be used to oppose the ipu/ipd while meeting the above criteria. users should confirm this resistor value is correct for their specific application. for most systems, a 20-k w resistor can be used to compliment the ipu/ipd on the device configuration pins while meeting the above criteria. users should confirm this resistor value is correct for their specific application. for more detailed information on input current (i i ), and the low-/high-level input voltages (v il and v ih ) for the c6454 device, see section 6.3 , electrical characteristics over recommended ranges of supply voltage and operating case temperature. to determine which pins on the c6454 device include internal pullup/pulldown resistors, see table 2-3 , terminal functions. device configuration 68 submit documentation feedback www.ti.com product preview
3.8 configuration examples TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 figure 3-12 and figure 3-13 illustrate examples of peripheral selections/options that are configurable on the c6454 device. figure 3-12. configuration example a (mcbsp + hpi32 + i2c + emifa + ddr2 memory controller + timers + emac (mii) + mdio) submit documentation feedback device configuration 69 product preview www.ti.com shading denotes a peripheral module not available for this configuration. mcbsp0 timer0 emifa gpio pll2 and pll2 controller timer1 pll1 and pll1 controller ddr2 emif aed[63:0] 64 aeclkin, aardy , ahold aea[22:3], ace[3:0] , abe[7:0] , aeclkout , asdcke, aholda , abusreq, asads /asre , aaoe /asoe , aa we /aswe sclsda clkin1, pll v1 sysclk4 hrdy , hint hcntl0, hcntl1, hhwil, has , hr/w , hcs , hds1 , hds2 clkr0, fsr0, dr0, clks0, dx0, fsx0, clkx0 mrxd[7:0], mrxer, mrxdv , mcol, mcrs, mtclk, mrclk 32 hd[31:0] clkin2, pll v2 gp[15:12,2,1] dea[21:2], dce[1:0] , dbe[3:0] , ddrclk, ddrclk , dsdcke, ddqs, ddqs , dsdcas , dsdras , dsdwe aea[19:16] (bootmode[3:0]) = 0001, (hpi boot)aea[15] (aeclkin_sel) = 0, (aeclkin, default) aea[14] (hpi_width) = 1, (hpi, 32-bit operation) aea[13] (lendian) = ipu, (little endian mode, default) aea[12] = 0, (do not oppose ipd) aea[1 1] = 0, (do not oppose ipd) aea[10:9] (macsel[1:0]) = 00, (10/100 mii mode) aea[8] (pci_eeai) = 0, (pci i2c eeprom auto-init disabled, default)aea[7] = 0, (do not oppose ipd) aea[6] (pci66) = 0, (pci 33 mhz [default, don't care]) aea[5] (mcbsp1_en) = 0, (mcbsp1 disabled, default) aea[4] (sysclkout_en) = 1, (sysclk4 pin function) aea[3] = 0, (do not oppose ipd) aea[2:0] (cfggp[2:0]) = 000, (default) mcbsp1 emac 32 ed[31:0] tinp1l tout1l tout0 tinp0 mtxd[7:0], mtxen, mdio, mdclk mdio i2c pci hpi (32-bit) devsta t register: 0x0061 8161 pci_en = 0 (pci disabled, default)aba1 (emif a_en) = 1(emif a enabled) aba0 (ddr2_en) = 1 (ddr2 memory controller enabled)
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 figure 3-13. configuration example b (2 mcbsps + hpi32 + i2c + emifa + ddr2 memory controller + timers + emac (gmii) + mdio 70 device configuration submit documentation feedback www.ti.com product preview shading denotes a peripheral module not available for this configuration. mcbsp0 timer0 emifa gpio timer1 pll1 and pll1 controller ddr2 emif aed[63:0] 64 aeclkin, aardy , ahold aea[22:3], ace[3:0] , abe[7:0] , aeclkout , asdcke, aholda , abusreq, asads /asre , aaoe /asoe , aawe /aswe sclsda clkin1, pll v1 sysclk4 hrdy , hint hcntl0, hcntl1, hhwil, has , hr/w , hcs , hds1 , hds2 clkr0, fsr0, dr0, clks0, dx0, fsx0, clkx0 mrxd[7:0], mrxer, mrxdv , mcol, mcrs, mtclk, mrclk 32 hd[31:0] clkin2, pll v2 gp[15:12,2,1] dea[21:2], dce[1:0] , dbe[3:0] , ddrclk, ddrclk , dsdcke, ddqs, ddqs , dsdcas , dsdras , dsdwe aea[19:16] (bootmode[3:0]) = 0001, (hpi boot)aea[15] (aeclkin_sel) = 0, (aeclkin, default) aea[14] (hpi_width) = 1, (hpi, 32-bit operation) aea[13] (lendian) = ipu, (little endian mode, default) aea[12] = 0, (do not oppose ipd) aea[1 1] = 0, (do not oppose ipd) aea[10:9] (macsel[1:0]) = 00, (10/100 mii mode) aea[8] (pci_eeai) = 0, (pci i2c eeprom auto-init disabled, default)aea[7] = 0, (do not oppose ipd) aea[6] (pci66) = 0, (pci 33 mhz [default, don't care]) aea[5] (mcbsp1_en) = 1, (mcbsp1 enabled) aea[4] (sysclkout_en) = 1, (sysclk4 pin function) aea[3] = 0, (do not oppose ipd) aea[2:0] (cfggp[2:0]) = 000, (default) mcbsp1 emac 32 ed[31:0] tinp1l tout1l tout0 tinp0 mtxd[7:0], mtxen, mdio, mdclk mdio i2c pci hpi (32-bit) clkr1, fsr1, dr1, clks1, dx1, fsx1, clkx1 devsta t register: 0x0061 c161 pci_en = 0 (pci disabled, default)aba1 (emif a_en) = 1(emif a enabled) aba0 (ddr2_en) = 1 (ddr2 memory controller enabled) pll2 and pll2 controller
4 system interconnect 4.1 internal buses, bridges, and switch fabrics TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 on the c6454 device, the c64x+ megamodule, the edma3 transfer controllers, and the system peripherals are interconnected through two switch fabrics. the switch fabrics allow for low-latency, concurrent data transfers between master peripherals and slave peripherals. through a switch fabric the cpu can send data to the emifa without affecting a data transfer between the pci and the ddr2 memory controller. the switch fabrics also allow for seamless arbitration between the system masters when accessing system slaves. two types of buses exist in the c6454 device: data buses and configuration buses. some c6454 peripherals have both a data bus and a configuration bus interface, while others only have one type of interface. furthermore, the bus interface width and speed varies from peripheral to peripheral. configuration buses are mainly used to access the register space of a peripheral and the data buses are used mainly for data transfers. however, in some cases, the configuration bus is also used to transfer data. for example, data is transferred to the mcbsp via its configuration bus. similarly, the data bus can also be used to access the register space of a peripheral. for example, the emifa and ddr2 memory controller registers are accessed through their data bus interface. the c64x+ megamodule, the edma3 traffic controllers, and the various system peripherals can be classified into two categories: masters and slaves. masters are capable of initiating read and write transfers in the system and do not rely on the edma3 for their data transfers. slaves on the other hand rely on the edma3 to perform transfers to and from them. masters include the edma3 traffic controllers and pci. slaves include the mcbsp and i2c. the c6454 device contains two switch fabrics through which masters and slaves communicate. the data switch fabric, known as the data switched central resource (scr), is a high-throughput interconnect mainly used to move data across the system (for more information, see section 4.2 ). the data scr connects masters to slaves via 128-bit data buses running at a sysclk2 frequency (sysclk2 is generated from pll1 controller). peripherals that have a 128-bit data bus interface running at this speed can connect directly to the data scr; other peripherals require a bridge. the configuration switch fabric, also known as the configuration switch central resource (scr) is mainly used by the c64x+ megamodule to access peripheral registers (for more information, see section 4.3 ). the configuration scr connects c64x+ megamodule to slaves via 32-bit configuration buses running at a sysclk2 frequency (sysclk2 is generated from pll1 controller). as with the data scr, some peripherals require the use of a bridge to interface to the configuration scr. note that the data scr also connects to the configuration scr. bridges perform a variety of functions: conversion between configuration bus and data bus. width conversion between peripheral bus width and scr bus width. frequency conversion between peripheral bus frequency and scr bus frequency. for example, the emifa and ddr2 memory controller require a bridge to convert their 64-bit data bus interface into a 128-bit interface so that they can connect to the data scr. note that some peripherals can be accessed through the data scr and also through the configuration scr. submit documentation feedback system interconnect 71 product preview www.ti.com
4.2 data switch fabric connections TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 figure 4-1 shows the connection between slaves and masters through the data switched central resource (scr). masters are shown on the right and slaves on the left. the data scr connects masters to slaves via 128-bit data buses running at a sysclk2 frequency. sysclk2 is supplied by the pll1 controller and is fixed at a frequency equal to the cpu frequency divided by 3. some peripherals, like pci and the c64x+ megamodule, have both slave and master ports. note that each edma3 transfer controller has an independent connection to the data scr. note that masters can access the configuration scr through the data scr. the configuration scr is described in section 4.3 . not all masters on the c6454 dsp may connect to all slaves. allowed connections are summarized in table 4-1 . system interconnect 72 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 figure 4-1. switched central resource block diagram submit documentation feedback system interconnect 73 product preview www.ti.com emac hpi m m 128-bit (sysclk2) m3 m0 s m m m mcbsps s ddr2 memory controller s emifa s pci s master s m bridge cfgscr s bridge pci m edma3 channel controller edma3 transfer controllers megamodule m1 m2 s3 s0s1 s2 s s events m megamodule data scr 128 (sysclk2)128 (sysclk2) 128 (sysclk2) 128 (sysclk2) 32 (sysclk3) 32 (sysclk3) 32 (sysclk3) 32(sysclk3) 128 (sysclk2) 128 (sysclk2) bridge 128 (sysclk3) bridge bridge 128 (sysclk2) 128 (sysclk2) 64 (sysclk2) 64 (sysclk2) 32 (sysclk2) configuration bus data bus 128 (sysclk2) m 32 (sysclk3) 128 (sysclk2) 32 (sysclk3) 32 (sysclk3)
4.3 configuration switch fabric TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 4-1. scr connection matrix ddr2 memory mcbsps configuration scr pci emifa megamodule controller tc0 n n n y y y tc1 y y y y y y tc2 n n y y y y tc3 n n y y y y emac n n n y y y hpi n y n y y y pci n y n y y y figure 4-2 shows the connection between the c64x+ megamodule and the configuration switched central resource (scr). the configuration scr is mainly used by the c64x+ megamodule to access peripheral registers. the data scr also has a connection to the configuration scr which allows masters to access most peripheral registers. the only registers not accessible by the data scr through the configuration scr are the device configuration registers and the pll1 and pll2 controller registers; these can only be accessed by the c64x+ megamodule. the configuration scr uses 32-bit configuration buses running at sysclk2 frequency. sysclk2 is supplied by the pll1 controller and is fixed at a frequency equal to the cpu frequency divided by 3. system interconnect 74 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 figure 4-2. c64x+ megamodule - scr connection submit documentation feedback system interconnect 75 product preview www.ti.com megamodule m cfg scr s m mcbsps s timers s hpi s pci s s bridge 7 gpio s emac/mdio m data scr s s i2c s s pll controllers (a) s s device configuration registers (a) edma3 tc0 s edma3 tc1 s s edma3 tc2 s edma3 cc s s edma3 tc3 s m 32 (sysclk3) mux 32 (sysclk2) 32 (sysclk2) 32 (sysclk2) 32 (sysclk3) 32 (sysclk2) 32 (sysclk2) 32-bit (sysclk2) configuration busdata bus mux 32 (sysclk2) 32 (sysclk2) 32 (sysclk2) 32 (sysclk2) a. only accessible by the c64x+ megamodule. b. all clocks in this figure are generated by the pll1 controller . 32 (sysclk3) 32 (sysclk3) 32 (sysclk3) 32 (sysclk3) 32 (sysclk3) 32 (sysclk3) 32 (sysclk3) 32 (sysclk3)
4.4 priority allocation TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 on the c6454 device, each of the masters (excluding the c64x+ megamodule) are assigned a priority via the priority allocation register (pri_alloc), see figure 4-3 . the priority is enforced when several masters in the system are vying for the same endpoint. a value of 000b has the highest priority, while 111b has the lowest priority. note that the configuration scr port on the data scr is considered a single endpoint meaning priority will be enforced when multiple masters try to access the configuration scr. priority is also enforced on the configuration scr side when a master (through the data scr) tries to access the same endpoint as the c64x+ megamodule. other master peripherals are not present in the pri_alloc register as they have their own registers to program their priorities. for more information on the default priority values in these peripheral registers, see the device-compatible peripheral reference guides. ti recommends that these priority registers be reprogrammed upon initial use. 31 16 reserved r-0000 0000 0000 0000 15 12 11 9 8 6 5 3 2 0 reserved reserved reserved host emac r-000 0 r/w-001 r-0 r/w-010 r/w-001 legend: r/w = read/write; r = read only; -n = value at reset figure 4-3. priority allocation register (pri_alloc) system interconnect 76 submit documentation feedback www.ti.com product preview
5 c64x+ megamodule 5.1 memory architecture TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the c64x+ megamodule consists of several components ? the c64x+ cpu, the l1 program and data memory controllers, the l2 memory controller, the internal dma (idma), the interrupt controller, power-down controller, and external memory controller. the c64x+ megamodule also provides support for memory protection (for l1p, l1d, and l2 memories) and bandwidth management (for resources local to the c64x+ megamodule). figure 5-1 shows a block diagram of the c64x+ megamodule. figure 5-1. 64x+ megamodule block diagram for more detailed information on the tms320c64x+ megamodule on the c6454 device, see the tms320c64x+ megamodule reference guide (literature number spru871 ). the TMS320C6454 device contains a 1048kb level-2 memory (l2), a 32kb level-1 program memory (l1p), and a 32kb level-1 data memory (l1d). the l1p memory configuration for the c6454 device is as follows: region 0 size is 0k bytes (disabled). region 1 size is 32k bytes with no wait states. the l1d memory configuration for the c6454 device is as follows: region 0 size is 0k bytes (disabled). submit documentation feedback c64x+ megamodule 77 product preview www.ti.com a register file data path 1 data path 2 b register file d2 s2 xx xx m2 l2 instruction decode m1 xxxx l1 s1 d1 16/32?bit instruction dispatch instruction fetch sploop buf fer 64 64 c64x+ cpu 256 32 l1d cache/sram bandwidth management memory protection l1 data memory controller idma 256 256 bandwidth management l1 program memory controller memory protection 256 advanced event triggering (aet) interrupt and exception controller power control l2 memory controller 256 256 master dma slave dma 128 256 l1p cache/sram l2 cache/ sram 256 128 128 t o primary switch fabric cache control bandwidth management memory protection cache control cache control internal rom (a) 256 configuration registers 32 t o chip registers external memory controller a. when accessing the internal rom of the dsp , the cpu frequency must always be less than 750 mhz.
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 region 1 size is 32k bytes with no wait states. l1d is a two-way set-associative cache while l1p is a direct-mapped cache. the l1p and l1d cache can be reconfigured via software through the l1pmode field of the l1p configuration register (l1pmode) and the l1dmode field of the l1d configuration register (l1dcfg) of the c64x+ megamodule. after device reset, l1p and l1d cache are configured as all cache or all sram. the on-chip bootloader changes the reset configuration for l1p and l1d. for more information, see the tms320c645x bootloader user's guide (literature number spruec6 ). figure 5-2 and figure 5-3 show the available sram/cache configurations for l1p and l1d, respectively. figure 5-2. TMS320C6454 l1p memory configurations figure 5-3. TMS320C6454 l1d memory configurations c64x+ megamodule 78 submit documentation feedback www.ti.com product preview 4k bytes 8k bytes 16k bytes l1p memory 00e0 0000h 00e0 4000h 00e0 6000h 00e0 7000h 00e0 8000h direct mapped sram 1/2 dm 3/4 sram sram 7/8 all sram 000 001 010 011 100 block baseaddress l1p mode bits cache 4k bytes cache direct mapped cache direct mapped cache 4k bytes 8k bytes 16k bytes l1d memory 00f0 0000h 00f0 4000h 00f0 6000h 00f0 7000h 00f0 8000h 2-way sram 1/2 2-way 3/4 sram sram 7/8 all sram 000 001 010 011 100 block baseaddress l1d mode bits cache 4k bytes cache 2-waycache 2-waycache
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the l2 memory configuration for the c6454 device is as follows: port 0 configuration: ? memory size is 1048kb ? starting address is 0080 0000h ? 2-cycle latency ? 4 128-bit bank configuration port 1 configuration: ? memory size is 32k bytes (this corresponds to the internal rom) ? starting address is 0010 0000h ? 1-cycle latency ? 1 256-bit bank configuration l2 memory can be configured as all sram or as part 4-way set-associative cache. the amount of l2 memory that is configured as cache is controlled through the l2mode field of the l2 configuration register (l2cfg) of the c64x+ megamodule. figure 5-4 shows the available sram/cache configurations for l2. by default, l2 is configured as all sram after device reset. figure 5-4. TMS320C6454 l2 memory configurations for more information on the operation l1 and l2 caches, see the tms320c64x+ dsp cache user's guide (literature number spru862 ). all memory on the c6454 has a unique location in the memory map (see table 2-2 , c6454 memory map summary). when accessing the internal rom of the dsp, the cpu frequency must always be less than 750 mhz. therefore, when using a software boot mode, care must be taken such that the cpu frequency does not exceed 750 mhz at any point during the boot sequence. after the boot sequence has completed, the cpu frequency can be programmed to the frequency required by the application. for more detailed information ont he boot modes, see section 2.4 , boot sequence. submit documentation feedback c64x+ megamodule 79 product preview www.ti.com 32k bytes 32k bytes 64k bytes 128k bytes 792k bytes l2 memory 0080 0000h 008c 0000h 008e 0000h 008f 0000h 008f 8000h 0090 0000h 3/4 sram 4-waycache 4-waycache sram 7/8 4-way 15/16 sram 4-way sram 31/32 all sram 000 001 010 011 111 block baseaddress l2 mode bits cache
5.2 memory protection 5.3 bandwidth management TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 memory protection allows an operating system to define who or what is authorized to access l1d, l1p, and l2 memory. to accomplish this, the l1d, l1p, and l2 memories are divided into pages. there are 16 pages of l1p (2kb each), 16 pages of l1d (2kb each), and 16 pages of l2 (64kb each). the l1d, l1p, and l2 memory controllers in the c64x+ megamodule are equipped with a set of registers that specify the permissions for each memory page. each page may be assigned with fully orthogonal user and supervisor read, write, and execute permissions. additionally, a page may be marked as either (or both) locally or globally accessible. a local access is a direct cpu access to l1d, l1p, and l2, while a global access is initiated by a dma (either idma or the edma3) or by other system masters. note that edma or idma transfers programmed by the cpu count as global accesses. the cpu and the system masters on the c6454 device are all assigned a privilege id of 0. therefore it is only possible to specify whether memory pages are locally or globally accessible. the aid0 and local bits of the memory protection page attribute registers specify the memory page protection scheme, see table 5-1 . table 5-1. available memory page protection schemes aid0 bit local bit description 0 0 no access to memory page is permitted. 0 1 only direct access by cpu is permitted. 1 0 only accesses by system masters and idma are permitted (includes edma and idma accesses initiated by the cpu). 1 1 all accesses permitted for more information on memory protection for l1d, l1p, and l2, see the tms320c64x+ megamodule reference guide (literature number spru871 ). when multiple requestors contend for a single c64x+ megamodule resource, the conflict is solved by granting access to the highest priority requestor. the following four resources are managed by the bandwidth management control hardware: level 1 program (l1p) sram/cache level 1 data (l1d) sram/cache level 2 (l2) sram/cache memory-mapped registers configuration bus the priority level for operations initiated within the c64x+ megamodule; e.g., cpu-initiated transfers, user-programmed cache coherency operations, and idma-initiated transfers, are declared through registers in the c64x+ megamodule. the priority level for operations initiated outside the c64x+ megamodule by system peripherals is declared through the priority allocation register (pri_alloc), see section 4.4 . system peripherals with no fields in pri_alloc have their own registers to program their priorities. more information on the bandwidth management features of the c64x+ megamodule can be found in the tms320c64x+ megamodule reference guide (literature number spru871 ). c64x+ megamodule 80 submit documentation feedback www.ti.com product preview
5.4 power-down control 5.5 megamodule resets TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the c64x+ megamodule supports the ability to power-down various parts of the c64x+ megamodule. the power-down controller (pdc) of the c64x+ megamodule can be used to power down l1p, the cache control hardware, the cpu, and the entire c64x+ megamodule. these power-down features can be used to design systems for lower overall system power requirements. note the c6454 does not support power-down modes for the l2 memory at this time. more information on the power-down features of the c64x+ megamodule can be found in the tms320c64x+ megamodule reference guide (literature number spru871 ). table 5-2 shows the reset types supported on the c6454 device and they affect the resetting of the megamodule, either both globally or just locally. table 5-2. megamodule reset (global or local) global local reset type megamodule megamodule reset reset power-on reset y y warm reset y y system reset y y cpu reset n y for more detailed information on the global and local megamodule resets, see the tms320c64x+ megamodule reference guide (literature number spru871 ). and for more detailed information on device resets, see section 7.6 , reset controller. submit documentation feedback c64x+ megamodule 81 product preview www.ti.com
5.6 megamodule revision TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the version and revision of the c64x+ megamodule can be read from the megamodule revision id register (mm_revid) located at address 0181 2000h. the mm_revid register is shown in figure 5-5 and described in table 5-3 . the c64x+ megamodule revision is dependant on the silicon revision being used. for more information, see the tms320c6455/54 digital signal processor silicon errata (literature number sprz234 ). 31 16 15 0 version revision (a) r-1h r-n legend: r = read only; - n = value after reset a. the c64x+ megamodule revision is dependant on the silicon revision being used. for more information, see the tms320c6455/54 digital signal processor silicon errata (literature number sprz234 ). figure 5-5. megamodule revision id register (mm_revid) [hex address: 0181 2000h] table 5-3. megamodule revision id register (mm_revid) field descriptions bit field value description 31:16 version 1h version of the c64x+ megamodule implemented on the device. this field is always read as 1h. 15:0 revision revision of the c64x+ megamodule version implemented on the device. the c64x+ megamodule revision is dependant on the silicon revision being used. for more information, see the tms320c6455/54 digital signal processor silicon errata (literature number sprz234 ). c64x+ megamodule 82 submit documentation feedback www.ti.com product preview
5.7 c64x+ megamodule register description(s) TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 5-4. megamodule interrupt registers hex address range acronym register name 0180 0000 evtflag0 event flag register 0 (events [31:0]) 0180 0004 evtflag1 event flag register 1 0180 0008 evtflag2 event flag register 2 0180 000c evtflag3 event flag register 3 0180 0010 - 0180 001c - reserved 0180 0020 evtset0 event set register 0 (events [31:0]) 0180 0024 evtset1 event set register 1 0180 0028 evtset2 event set register 2 0180 002c evtset3 event set register 3 0180 0030 - 0180 003c - reserved 0180 0040 evtclr0 event clear register 0 (events [31:0]) 0180 0044 evtclr1 event clear register 1 0180 0048 evtclr2 event clear register 2 0180 004c evtclr3 event clear register 3 0180 0050 - 0180 007c - reserved 0180 0080 evtmask0 event mask register 0 (events [31:0]) 0180 0084 evtmask1 event mask register 1 0180 0088 evtmask2 event mask register 2 0180 008c evtmask3 event mask register 3 0180 0090 - 0180 009c - reserved 0180 00a0 mevtflag0 masked event flag status register 0 (events [31:0]) 0180 00a4 mevtflag1 masked event flag status register 1 0180 00a8 mevtflag2 masked event flag status register 2 0180 00ac mevtflag3 masked event flag status register 3 0180 00b0 - 0180 00bc - reserved 0180 00c0 expmask0 exception mask register 0 (events [31:0]) 0180 00c4 expmask1 exception mask register 1 0180 00c8 expmask2 exception mask register 2 0180 00cc expmask3 exception mask register 3 0180 00d0 - 0180 00dc - reserved 0180 00e0 mexpflag0 masked exception flag register 0 0180 00e4 mexpflag1 masked exception flag register 1 0180 00e8 mexpflag2 masked exception flag register 2 0180 00ec mexpflag3 masked exception flag register 3 0180 00f0 - 0180 00fc - reserved 0180 0100 - reserved 0180 0104 intmux1 interrupt multiplexor register 1 0180 0108 intmux2 interrupt multiplexor register 2 0180 010c intmux3 interrupt multiplexor register 3 0180 0110 - 0180 013c - reserved 0180 0140 aegmux0 advanced event generator mux register 0 0180 0144 aegmux1 advanced event generator mux register 1 0180 0148 - 0180 017c - reserved 0180 0180 intxstat interrupt exception status register submit documentation feedback c64x+ megamodule 83 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 5-4. megamodule interrupt registers (continued) hex address range acronym register name 0180 0184 intxclr interrupt exception clear register 0180 0188 intdmask dropped interrupt mask register 0180 0188 - 0180 01bc - reserved 0180 01c0 evtasrt event asserting register 0180 01c4 - 0180 ffff - reserved table 5-5. megamodule powerdown control registers hex address range acronym register name 0181 0000 pdccmd power-down controller command register 0181 0004 - 0181 1fff - reserved table 5-6. megamodule revision register hex address range acronym register name 0181 2000 mm_revid megamodule revision id register 0181 2004 ? 0181 2fff - reserved table 5-7. megamodule idma registers hex address range acronym register name 0182 0000 idma0stat idma channel 0 status register 0182 0004 idma0mask idma channel 0 mask register 0182 0008 imda0src idma channel 0 source address register 0182 000c idma0dst idma channel 0 destination address register 0182 0010 idma0cnt idma channel 0 count register 0182 0014 - 0182 00fc - reserved 0182 0100 idma1stat idma channel 1 status register 0182 0104 - reserved 0182 0108 imda1src idma channel 1 source address register 0182 010c idma1dst idma channel 1 destination address register 0182 0110 idma1cnt idma channel 1 count register 0182 0114 - 0182 017c - reserved 0182 0180 - reserved 0182 0184 - 0182 01ff - reserved c64x+ megamodule 84 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 5-8. megamodule cache configuration registers hex address range acronym register name 0184 0000 l2cfg l2 cache configuration register 0184 0004 - 0184 001f - reserved 0184 0020 l1pcfg l1p configuration register 0184 0024 l1pcc l1p cache control register 0184 0028 - 0184 003f - reserved 0184 0040 l1dcfg l1d configuration register 0184 0044 l1dcc l1d cache control register 0184 0048 - 0184 0fff - reserved 0184 1000 - 0184 104f - see table 5-10 , cpu megamodule bandwidth management registers 0184 1050 - 0184 3fff - reserved 0184 4000 l2wbar l2 writeback base address register - for block writebacks 0184 4004 l2wwc l2 writeback word count register 0184 4008 - 0184 400c - reserved 0184 4010 l2wibar l2 writeback and invalidate base address register - for block writebacks 0184 4014 l2wiwc l2 writeback and invalidate word count register 0184 4018 l2ibar l2 invalidate base address register 0184 401c l2iwc l2 invalidate word count register 0184 4020 l1pibar l1p invalidate base address register 0184 4024 l1piwc l1p invalidate word count register 0184 4030 l1dwibar l1d writeback and invalidate base address register 0184 4034 l1dwiwc l1d writeback and invalidate word count register 0184 4038 - reserved 0184 4040 l1dwbar l1d writeback base address register - for block writebacks 0184 4044 l1dwwc l1d writeback word count register 0184 4048 l1dibar l1d invalidate base address register 0184 404c l1diwc l1d invalidate word count register 0184 4050 - 0184 4fff - reserved 0184 5000 l2wb l2 global writeback register 0184 5004 l2wbinv l2 global writeback and invalidate register 0184 5008 l2inv l2 global invalidate register 0184 500c - 0184 5024 - reserved 0184 5028 l1pinv l1p global invalidate register 0184 502c - 0184 503c - reserved 0184 5040 l1dwb l1d global writeback register 0184 5044 l1dwbinv l1d global writeback and invalidate register 0184 5048 l1dinv l1d global invalidate register mar0 to 0184 8000 - 0184 81fc reserved mar127 mar128 to 0184 8200 - 0184 823c reserved mar143 mar144 to 0184 8240 - 0184 827c reserved mar159 0184 8280 mar160 controls emifa ce2 range a000 0000 - a0ff ffff 0184 8284 mar161 controls emifa ce2 range a100 0000 - a1ff ffff 0184 8288 mar162 controls emifa ce2 range a200 0000 - a2ff ffff 0184 828c mar163 controls emifa ce2 range a300 0000 - a3ff ffff 0184 8290 mar164 controls emifa ce2 range a400 0000 - a4ff ffff submit documentation feedback c64x+ megamodule 85 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 5-8. megamodule cache configuration registers (continued) hex address range acronym register name 0184 8294 mar165 controls emifa ce2 range a500 0000 - a5ff ffff 0184 8298 mar166 controls emifa ce2 range a600 0000 - a6ff ffff 0184 829c mar167 controls emifa ce2 range a700 0000 - a7ff ffff 0184 82a0 mar168 controls emifa ce2 range a800 0000 - a8ff ffff 0184 82a4 mar169 controls emifa ce2 range a900 0000 - a9ff ffff 0184 82a8 mar170 controls emifa ce2 range aa00 0000 - aaff ffff 0184 82ac mar171 controls emifa ce2 range ab00 0000 - abff ffff 0184 82b0 mar172 controls emifa ce2 range ac00 0000 - acff ffff 0184 82b4 mar173 controls emifa ce2 range ad00 0000 - adff ffff 0184 82b8 mar174 controls emifa ce2 range ae00 0000 - aeff ffff 0184 82bc mar175 controls emifa ce2 range af00 0000 - afff ffff 0184 82c0 mar176 controls emifa ce3 range b000 0000 - b0ff ffff 0184 82c4 mar177 controls emifa ce3 range b100 0000 - b1ff ffff 0184 82c8 mar178 controls emifa ce3 range b200 0000 - b2ff ffff 0184 82cc mar179 controls emifa ce3 range b300 0000 - b3ff ffff 0184 82d0 mar180 controls emifa ce3 range b400 0000 - b4ff ffff 0184 82d4 mar181 controls emifa ce3 range b500 0000 - b5ff ffff 0184 82d8 mar182 controls emifa ce3 range b600 0000 - b6ff ffff 0184 82dc mar183 controls emifa ce3 range b700 0000 - b7ff ffff 0184 82e0 mar184 controls emifa ce3 range b800 0000 - b8ff ffff 0184 82e4 mar185 controls emifa ce3 range b900 0000 - b9ff ffff 0184 82e8 mar186 controls emifa ce3 range ba00 0000 - baff ffff 0184 82ec mar187 controls emifa ce3 range bb00 0000 - bbff ffff 0184 82f0 mar188 controls emifa ce3 range bc00 0000 - bcff ffff 0184 82f4 mar189 controls emifa ce3 range bd00 0000 - bdff ffff 0184 82f8 mar190 controls emifa ce3 range be00 0000 - beff ffff 0184 82fc mar191 controls emifa ce3 range bf00 0000 - bfff ffff 0184 8300 mar192 controls emifa ce4 range c000 0000 - c0ff ffff 0184 8304 mar193 controls emifa ce4 range c100 0000 - c1ff ffff 0184 8308 mar194 controls emifa ce4 range c200 0000 - c2ff ffff 0184 830c mar195 controls emifa ce4 range c300 0000 - c3ff ffff 0184 8310 mar196 controls emifa ce4 range c400 0000 - c4ff ffff 0184 8314 mar197 controls emifa ce4 range c500 0000 - c5ff ffff 0184 8318 mar198 controls emifa ce4 range c600 0000 - c6ff ffff 0184 831c mar199 controls emifa ce4 range c700 0000 - c7ff ffff 0184 8320 mar200 controls emifa ce4 range c800 0000 - c8ff ffff 0184 8324 mar201 controls emifa ce4 range c900 0000 - c9ff ffff 0184 8328 mar202 controls emifa ce4 range ca00 0000 - caff ffff 0184 832c mar203 controls emifa ce4 range cb00 0000 - cbff ffff 0184 8330 mar204 controls emifa ce4 range cc00 0000 - ccff ffff 0184 8334 mar205 controls emifa ce4 range cd00 0000 - cdff ffff 0184 8338 mar206 controls emifa ce4 range ce00 0000 - ceff ffff 0184 833c mar207 controls emifa ce4 range cf00 0000 - cfff ffff 0184 8340 mar208 controls emifa ce5 range d000 0000 - d0ff ffff 0184 8344 mar209 controls emifa ce5 range d100 0000 - d1ff ffff 0184 8348 mar210 controls emifa ce5 range d200 0000 - d2ff ffff 0184 834c mar211 controls emifa ce5 range d300 0000 - d3ff ffff c64x+ megamodule 86 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 5-8. megamodule cache configuration registers (continued) hex address range acronym register name 0184 8350 mar212 controls emifa ce5 range d400 0000 - d4ff ffff 0184 8354 mar213 controls emifa ce5 range d500 0000 - d5ff ffff 0184 8358 mar214 controls emifa ce5 range d600 0000 - d6ff ffff 0184 835c mar215 controls emifa ce5 range d700 0000 - d7ff ffff 0184 8360 mar216 controls emifa ce5 range d800 0000 - d8ff ffff 0184 8364 mar217 controls emifa ce5 range d900 0000 - d9ff ffff 0184 8368 mar218 controls emifa ce5 range da00 0000 - daff ffff 0184 836c mar219 controls emifa ce5 range db00 0000 - dbff ffff 0184 8370 mar220 controls emifa ce5 range dc00 0000 - dcff ffff 0184 8374 mar221 controls emifa ce5 range dd00 0000 - ddff ffff 0184 8378 mar222 controls emifa ce5 range de00 0000 - deff ffff 0184 837c mar223 controls emifa ce5 range df00 0000 - dfff ffff 0184 8380 mar224 controls ddr2 ce0 range e000 0000 - e0ff ffff 0184 8384 mar225 controls ddr2 ce0 range e100 0000 - e1ff ffff 0184 8388 mar226 controls ddr2 ce0 range e200 0000 - e2ff ffff 0184 838c mar227 controls ddr2 ce0 range e300 0000 - e3ff ffff 0184 8390 mar228 controls ddr2 ce0 range e400 0000 - e4ff ffff 0184 8394 mar229 controls ddr2 ce0 range e500 0000 - e5ff ffff 0184 8398 mar230 controls ddr2 ce0 range e600 0000 - e6ff ffff 0184 839c mar231 controls ddr2 ce0 range e700 0000 - e7ff ffff 0184 83a0 mar232 controls ddr2 ce0 range e800 0000 - e8ff ffff 0184 83a4 mar233 controls ddr2 ce0 range e900 0000 - e9ff ffff 0184 83a8 mar234 controls ddr2 ce0 range ea00 0000 - eaff ffff 0184 83ac mar235 controls ddr2 ce0 range eb00 0000 - ebff ffff 0184 83b0 mar236 controls ddr2 ce0 range ec00 0000 - ecff ffff 0184 83b4 mar237 controls ddr2 ce0 range ed00 0000 - edff ffff 0184 83b8 mar238 controls ddr2 ce0 range ee00 0000 - eeff ffff 0184 83bc mar239 controls ddr2 ce0 range ef00 0000 - efff ffff mar240 to 0184 83c0 -0184 83fc reserved mar255 table 5-9. megamodule l1/l2 memory protection registers hex address range acronym register name 0184 a000 l2mpfar l2 memory protection fault address register 0184 a004 l2mpfsr l2 memory protection fault status register 0184 a008 l2mpfcr l2 memory protection fault command register 0184 a00c - 0184 a0ff - reserved 0184 a100 l2mplk0 l2 memory protection lock key bits [31:0] 0184 a104 l2mplk1 l2 memory protection lock key bits [63:32] 0184 a108 l2mplk2 l2 memory protection lock key bits [95:64] 0184 a10c l2mplk3 l2 memory protection lock key bits [127:96] 0184 a110 l2mplkcmd l2 memory protection lock key command register 0184 a114 l2mplkstat l2 memory protection lock key status register 0184 a118 - 0184 a1ff - reserved 0184 a200 l2mppa0 l2 memory protection page attribute register 0 0184 a204 l2mppa1 l2 memory protection page attribute register 1 0184 a208 l2mppa2 l2 memory protection page attribute register 2 submit documentation feedback c64x+ megamodule 87 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 5-9. megamodule l1/l2 memory protection registers (continued) hex address range acronym register name 0184 a20c l2mppa3 l2 memory protection page attribute register 3 0184 a210 l2mppa4 l2 memory protection page attribute register 4 0184 a214 l2mppa5 l2 memory protection page attribute register 5 0184 a218 l2mppa6 l2 memory protection page attribute register 6 0184 a21c l2mppa7 l2 memory protection page attribute register 7 0184 a220 l2mppa8 l2 memory protection page attribute register 8 0184 a224 l2mppa9 l2 memory protection page attribute register 9 0184 a228 l2mppa10 l2 memory protection page attribute register 10 0184 a22c l2mppa11 l2 memory protection page attribute register 11 0184 a230 l2mppa12 l2 memory protection page attribute register 12 0184 a234 l2mppa13 l2 memory protection page attribute register 13 0184 a238 l2mppa14 l2 memory protection page attribute register 14 0184 a23c l2mppa15 l2 memory protection page attribute register 15 0184 a240 l2mppa16 l2 memory protection page attribute register 16 0184 a244 l2mppa17 l2 memory protection page attribute register 17 0184 a248 l2mppa18 l2 memory protection page attribute register 18 0184 a24c l2mppa19 l2 memory protection page attribute register 19 0184 a250 l2mppa20 l2 memory protection page attribute register 20 0184 a254 l2mppa21 l2 memory protection page attribute register 21 0184 a258 l2mppa22 l2 memory protection page attribute register 22 0184 a25c l2mppa23 l2 memory protection page attribute register 23 0184 a260 l2mppa24 l2 memory protection page attribute register 24 0184 a264 l2mppa25 l2 memory protection page attribute register 25 0184 a268 l2mppa26 l2 memory protection page attribute register 26 0184 a26c l2mppa27 l2 memory protection page attribute register 27 0184 a270 l2mppa28 l2 memory protection page attribute register 28 0184 a274 l2mppa29 l2 memory protection page attribute register 29 0184 a278 l2mppa30 l2 memory protection page attribute register 30 0184 a27c l2mppa31 l2 memory protection page attribute register 31 0184 a280 - 0184 a3ff - reserved 0184 a400 l1pmpfar l1 program (l1p) memory protection fault address register 0184 a404 l1pmpfsr l1p memory protection fault status register 0184 a408 l1pmpfcr l1p memory protection fault command register 0184 a40c - 0184 a4ff - reserved 0184 a500 l1pmplk0 l1p memory protection lock key bits [31:0] 0184 a504 l1pmplk1 l1p memory protection lock key bits [63:32] 0184 a508 l1pmplk2 l1p memory protection lock key bits [95:64] 0184 a50c l1pmplk3 l1p memory protection lock key bits [127:96] 0184 a510 l1pmplkcmd l1p memory protection lock key command register 0184 a514 l1pmplkstat l1p memory protection lock key status register 0184 a518 - 0184 abff - reserved 0184 ac00 l1dmpfar l1 data (l1d) memory protection fault address register 0184 ac04 l1dmpfsr l1d memory protection fault status register 0184 ac08 l1dmpfcr l1d memory protection fault command register 0184 ac0c - 0184 acff - reserved 0184 ad00 l1dmplk0 l1d memory protection lock key bits [31:0] 0184 ad04 l1dmplk1 l1d memory protection lock key bits [63:32] c64x+ megamodule 88 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 5-9. megamodule l1/l2 memory protection registers (continued) hex address range acronym register name 0184 ad08 l1dmplk2 l1d memory protection lock key bits [95:64] 0184 ad0c l1dmplk3 l1d memory protection lock key bits [127:96] 0184 ad10 l1dmplkcmd l1d memory protection lock key command register 0184 ad14 l1dmplkstat l1d memory protection lock key status register 0184 ad18 - 0185 ffff - reserved table 5-10. cpu megamodule bandwidth management registers hex address range acronym register name 0182 0200 emccpuarbe emc cpu arbitration control register 0182 0204 emcidmaarbe emc idma arbitration control register 0182 0208 emcsdmaarbe emc slave dma arbitration control register 0182 020c emcmdmaarbe emc master dma arbitration control resgiter 0182 0210 - 0182 02ff - reserved 0184 1000 l2dcpuarbu l2d cpu arbitration control register 0184 1004 l2didmaarbu l2d idma arbitration control register 0184 1008 l2dsdmaarbu l2d slave dma arbitration control register 0184 100c l2ducarbu l2d user coherence arbitration control resgiter 0184 1010 - 0184 103f - reserved 0184 1040 l1dcpuarbd l1d cpu arbitration control register 0184 1044 l1didmaarbd l1d idma arbitration control register 0184 1048 l1dsdmaarbd l1d slave dma arbitration control register 0184 104c l1ducarbd l1d user coherence arbitration control resgiter table 5-11. device configuration registers (chip-level registers) hex address range acronym register name comments read-only. provides status of the 02a8 0000 devstat device status register user's device configuration on reset. 02a8 0004 pri_alloc priority allocation register sets priority for master peripherals jtag and bsdl identification read-only. provides 32-bit jtag id of 02a8 0008 jtagid register the device. 02a8 000c - 02ab ffff - reserved 02ac 0000 - reserved 02ac 0004 perlock peripheral lock register 02ac 0008 percfg0 peripheral configuration register 0 02ac 000c - reserved 02ac 0010 - reserved 02ac 0014 perstat0 peripheral status register 0 02ac 0018 perstat1 peripheral status register 1 02ac 001c - 02ac 001f - reserved 02ac 0020 emaccfg emac configuration register 02ac 0024 - 02ac 002b - reserved 02ac 002c percfg1 peripheral configuration register 1 02ac 0030 - 02ac 0053 - reserved 02ac 0054 emubufpd emulator buffer powerdown register 02ac 0058 - reserved submit documentation feedback c64x+ megamodule 89 product preview www.ti.com
6 device operating conditions 6.1 absolute maximum ratings over operating case temperature range (unless otherwise 6.2 recommended operating conditions TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 noted) (1) supply voltage range: cv dd (2) -0.5 v to 1.5 v dv dd33 (2) -0.5 v to 4.2 v dv dd15 , dv dd18 , av dll1 , av dll2 (2) -0.5 v to 2.5 v pllv1, pllv2 (2) -0.5 v to 2.5 v input voltage (vi) range: 3.3-v pins (except pci-capable pins) -0.5 v to dv dd33 + 0.5 v pci-capable pins -0.5 v to dv dd33 + 0.5 v rgmii pins -0.5 v to 2.5 v ddr2 memory controller pins -0.5 v to 2.5 v output voltage (vo) range: 3.3-v pins (except pci-capable pins) -0.5 v to dv dd33 + 0.5 v pci-capable pins -0.5 v to dv dd33 + 0.5 v rgmii pins -0.5 v to 2.5 v ddr2 memory controller pins -0.5 v to 2.5 v operating case temperature range, t c : (default) 0c to 90c storage temperature range, t stg -65c to 150c (1) stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to v ss. min nom max unit -1000 1.2125 1.25 1.2875 v cv dd supply voltage, core -850 1.1640 1.20 1.2360 v -720 dv dd33 supply voltage, i/o 3.14 3.3 3.46 v dv dd18 supply voltage, i/o 1.71 1.8 1.89 v av dll1 supply voltage, i/o 1.71 1.8 1.89 v av dll2 supply voltage, i/o 1.71 1.8 1.89 v v refsstl reference voltage 0.49dv dd18 0.50dv dd18 0.51dv dd18 v 1.8-v operation 1.71 1.8 1.89 v supply voltage, i/o [required only dv dd15 for emac rgmii] 1.5-v operation 1.43 1.5 1.57 v 1.8-v operation 0.855 0.9 0.945 v v refhstl reference voltage 1.5-v operation 0.713 0.75 0.787 v pllv1, supply voltage, pll 1.71 1.8 1.89 v pllv2 v ss supply ground 0 0 0 v 3.3 v pins (except pci-capable and 2 v i2c pins) pci-capable pins 0.5dv dd33 dv dd33 + 0.5 v v ih high-level input voltage i2c pins 0.7dv dd33 v rgmii pins v refhstl + 0.10 dv dd15 + 0.30 v ddr2 memory controller pins v refsstl + 0.125 dv dd18 + 0.3 v (dc) device operating conditions 90 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 recommended operating conditions (continued) min nom max unit 3.3 v pins (except pci-capable and 0.8 v i2c pins) pci-capable pins -0.5 0.3dv dd33 v v il low-level input voltage i2c pins 0 0.3dv dd33 v rgmii pins -0.3 v refhstl - 0.1 v ddr2 memory controller pins -0.3 v refsstl - 0.125 v (dc) t c operating case temperature 0 90 c submit documentation feedback device operating conditions 91 product preview www.ti.com
6.3 electrical characteristics over recommended ranges of supply voltage and operating TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 case temperature (unless otherwise noted) parameter test conditions (1) min typ max unit 3.3-v pins (except dv dd33 = min, pci-capable and i2c 0.8dv dd33 v i oh = max pins) i oh = -0.5 ma, high-level pci-capable pins (2) 0.9dv dd33 v v oh dv dd33 = 3.3 v output voltage rgmii pins dv dd15 - 0.4 v ddr2 memory dv dd18 - 0.28 v controller pins 3.3-v pins (except dv dd33 = min, pci-capable and i2c 0.22dv dd33 v i ol = max pins) i ol = 1.5 ma, pci-capable pins (2) 0.1dv dd33 v dv dd33 = 3.3 v low-level output v ol voltage pulled up to 3.3 v, 3 ma sink i2c pins 0.4 v current rgmii pins 0.4 v ddr2 memory 0.28 v controller pins v i = v ss to dv dd33 , pins without internal pullup or -1 1 ua pulldown resistor 3.3-v pins (except pci-capable and i2c v i = v ss to dv dd33 , pins with 50 100 400 ua pins) internal pullup resistor input current i i (3) v i = v ss to dv dd33 , pins with [dc] -400 -100 -50 ua internal pulldown resistor i2c pins 0.1dv dd33 v i 0.9dv dd33 -10 10 ua pci-capable pins (4) -1000 1000 ua rgmii pins 0.4 v aeclkout, clkr1/gp[0], clkx1/gp[3], -8 ma sysclk4/gp[1], emu[18:0], clkr0, clkx0 emif pins (except aeclkout), nmi, tout0l, tinp0l, tout1l, tinp1l, pci_en, high-level emac-capable pins i oh output current (except rgmii pins), -4 ma [dc] resetstat, mcbsp-capable pins (except clkr1/gp[0], clkx1/gp[3], clkr0, clkx0), gp[7:4], and tdo pci-capable pins (2) -0.5 ma rgmii pins -8 ma ddr2 memory -13.4 ma controller pins (1) for test conditions shown as min, max, or nom, use the appropriate value specified in the recommended operating conditions table. (2) these rated numbers are from the pci local bus specification (version 2.3). the dc specification and ac specifications are defined in table 4-3 and table 4-4, respectively, of the pci local bus specification. (3) i i applies to input-only pins and bi-directional pins. for input-only pins, i i indicates the input leakage current. for bi-directional pins, i i includes input leakage current and off-state (hi-z) output leakage current. (4) pci input leakage currents include hi-z output leakage for all bidirectional buffers with 3-state outputs. device operating conditions 92 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) (continued) parameter test conditions (1) min typ max unit aeclkout, clkr1/gp[0], clkx1/gp[3], 8 ma sysclk4/gp[1], emu[18:0], clkr0, clkx0 emif pins (except aeclkout), nmi, tout0l, tinp0l, toutp1l, tinp1l, pci_en, low-level output emac-capable pins i ol current [dc] (except rgmii pins), 4 ma resetstat, mcbsp-capable pins (except clkr1/gp[0], clkx1/gp[3], clkr0, clkx0), gp[7:4], and tdo pci-capable pins (2) 1.5 ma rgmii pins 8 ma ddr2 memory 13.4 ma controller pins off-state output i oz (5) 3.3-v pins v o = dv dd33 or 0 v -20 20 ua current [dc] cv dd = 1.25 v, 1.57 w cpu frequency = 1000 mhz cv dd = 1.2 v, p cdd core supply power (6) 1.30 w cpu frequency = 850 mhz cv dd = 1.2 v, 1.18 w cpu frequency = 720 mhz dv dd33 = 3.3 v, dv dd18 = 1.8 v, pllv1 = pllv2 = av dll1 = 0.54 w av dll2 = 1.8 v, cpu frequency = 1000 mhz dv dd33 = 3.3 v, dv dd18 = 1.8 v, p ddd i/o supply power (6) pllv1 = pllv2 = av dll1 = 0.53 w av dll2 = 1.8 v, cpu frequency = 850 mhz dv dd33 = 3.3 v, dv dd18 = 1.8 v, pllv1 = pllv2 = av dll1 = 0.52 w av dll2 = 1.8 v, cpu frequency = 720 mhz c i input capacitance 10 pf c o output capacitance 10 pf (5) i oz applies to output-only pins, indicating off-state (hi-z) output leakage current. (6) assumes the following conditions: 60% cpu utilization; ddr2 at 50% utilization (250 mhz), 50% writes, 32 bits, 50% bit switching; two 2-mhz mcbsps at 100% utilization, 50% switching; two 75-mhz timers at 100% utilization; device configured for hpi32 mode with pull-up resistors on hpi pins; room temperature (25 c). the actual current draw is highly application-dependent. for more details on core and i/o activity, see the tms320c6455/54 power consumption summary application report (literature number spraae8 ). submit documentation feedback device operating conditions 93 product preview www.ti.com
7 c64x+ peripheral information and electrical specifications 7.1 parameter information 7.1.1 3.3-v signal transition levels 7.1.2 3.3-v signal transition rates TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 figure 7-1. test load circuit for ac timing measurements the load capacitance value stated is only for characterization and measurement of ac timing signals. this load capacitance value does not indicate the maximum load the device is capable of driving. all input and output timing parameters are referenced to 1.5 v for both "0" and "1" logic levels. figure 7-2. input and output voltage reference levels for ac timing measurements all rise and fall transition timing parameters are referenced to v il max and v ih min for input clocks, v ol max and v oh min for output clocks. figure 7-3. rise and fall transition time voltage reference levels all timings are tested with an input edge rate of 4 volts per nanosecond (4 v/ns). c64x+ peripheral information and electrical specifications 94 submit documentation feedback www.ti.com product preview t ransmission line 4.0 pf 1.85 pf z0 = 50 w (see note) tester pin electronics data sheet t iming reference point outputunder test note: the data sheet provides timing at the device pin. for output timing analysis, the tester pin electronics and its transmission line ef fects must be taken into account. a transmission line with a delay of 2 ns can be used to produce the desired transmission line ef fect. the transmission line is intended as a load only . it is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings. input requirements in this data sheet are tested with an input slew rate of < 4 v olts per nanosecond (4 v/ns) at the device pin. 42 w 3.5 nh device pin(see note) v ref = 1.5 v v ref = v il max (or v ol max) v ref = v ih min (or v oh min)
7.1.3 timing parameters and board routing analysis TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the timing parameter values specified in this data sheet do not include delays by board routings. as a good board design practice, such delays must always be taken into account. timing values may be adjusted by increasing/decreasing such delays. ti recommends utilizing the available i/o buffer information specification (ibis) models to analyze the timing characteristics correctly. to properly use ibis models to attain accurate timing analysis for a given system, see the using ibis models for timing analysis application report (literature number spra839 ). if needed, external logic hardware such as buffers may be used to compensate any timing differences. for inputs, timing is most impacted by the round-trip propagation delay from the dsp to the external device and from the external device to the dsp. this round-trip delay tends to negatively impact the input setup time margin, but also tends to improve the input hold time margins (see table 7-1 and figure 7-4 ). figure 7-4 represents a general transfer between the dsp and an external device. the figure also represents board route delays and how they are perceived by the dsp and the external device. table 7-1. board-level timing example (see figure 7-4 ) no. description 1 clock route delay 2 minimum dsp hold time 3 minimum dsp setup time 4 external device hold time requirement 5 external device setup time requirement 6 control signal route delay 7 external device hold time 8 external device access time 9 dsp hold time requirement 10 dsp setup time requirement 11 data route delay a. control signals include data for writes. b. data signals are generated during reads from an external device. figure 7-4. board-level input/output timings submit documentation feedback c64x+ peripheral information and electrical specifications 95 product preview www.ti.com 1 2 3 4 5 6 7 8 10 11 aeclkout (output from dsp) aeclkout (input to external device) control signals (a) (output from dsp) control signals (input to external device) data signals (b) (output from external device) data signals (b) (input to dsp) 9
7.2 recommended clock and control signal transition behavior 7.3 power supplies 7.3.1 power-supply sequencing 7.3.2 power-supply decoupling 7.3.3 power-down operation TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 all clocks and control signals must transition between v ih and v il (or between v il and v ih ) in a monotonic manner. ti recommends the power-supply sequence shown in figure 7-5 . after the dv dd33 supply is stable, the remaining power supplies can be powered up at the same time as cv dd as long as their supply voltage never exceeds the cv dd voltage during powerup. some ti power-supply devices include features that facilitate power sequencing; for example, auto-track or slow-start/enable features. for more information, visit www.ti.com/dsppower . figure 7-5. power-supply sequence table 7-2. timing requirements for power-supply sequence -720 -850 no. unit -1000 min max 1 t su(dvdd33-cvdd12) setup time, dv dd33 supply stable before cv dd12 supply stable 0.5 200 ms 2 t su(cvdd12-allsup) setup time, cv dd12 supply stable before all other supplies stable 0 200 ms in order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible close to the dsp. these caps need to be close to the dsp, no more than 1.25 cm maximum distance to be effective. physically smaller caps are better, such as 0402, but need to be evaluated from a yield/manufacturing point-of-view. parasitic inductance limits the effectiveness of the decoupling capacitors, therefore physically smaller capacitors should be used while maintaining the largest available capacitance value. as with the selection of any component, verification of capacitor availability over the product's production lifetime should be considered. one of the power goals for the c6454 is to reduce power dissipation due to unused peripherals. there are different ways to power down peripherals on the c6454 device. some peripherals can be statically powered down at device reset through the device configuration pins (see section 3.1 , device configuration at device reset). once in a static power-down state, the peripheral is held in reset and its clock is turned off. peripherals cannot be enabled once they are in a static power-down state. to take a peripheral out of the static power-down state, a device reset must be executed with a different configuration pin setting. after device reset, all peripherals on the c6454 device are in a disabled state and must be enabled by software before being used. it is possible to enable only the peripherals needed by the application while keeping the rest disabled. note that peripherals in a disabled state are held in reset with their clocks gated. for more information on how to enable peripherals, see section 3.3 , peripheral selection after device reset. c64x+ peripheral information and electrical specifications 96 submit documentation feedback www.ti.com product preview dv dd33 cv dd12 all other power supplies 1 2
7.3.4 preserving boundary-scan functionality on rgmii and ddr2 memory pins TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 peripherals used for booting, like i2c and hpi, are automatically enabled after device reset. it is not possible to disable these peripherals after the boot process is complete. the c64x+ megamodule also allows for software-driven power-down management for all of the c64x+ megamodule components through its power-down controller (pdc). the cpu can power-down part or the entire c64x+ megamodule through the power-down controller based on its own execution thread or in response to an external stimulus from a host or global controller. more information on the power-down features of the c64x+ megamodule can be found in the tms320c64x+ megamodule reference guide (literature number spru871 ). when the rgmii mode of the emac is not used, the dv dd15 , dv dd15mon , v refhstl , rsv13, and rsv14 pins can be connected directly to ground (v ss ) to save power. however, this will prevent boundary-scan from functioning on the rgmii pins of the emac. to preserve boundary-scan functionality on the rgmii pins, dv dd15 , v refhstl , rsv14, and rsv13 should be connected as follows: dv dd15 and dv dd15mon - connect these pins to the 1.8-v i/o supply (dv dd18 ). v refhstl - connect to a voltage of dv dd18 /2. the dv dd18 /2 voltage can be generated directly from the dv dd18 supply using two 1-k w resistors to form a resistor divider circuit. rsv13 - connect this pin to ground (v ss ) via a 200- w resistor. rsv14 - connect this pin to the 1.8-v i/o supply (dv dd18 ) via a 200- w resistor. similarly, when the ddr2 memory controller is not used, the v refsstl , rsv11, and rsv12 pins can be connected directly to ground (v ss ) to save power. however, this will prevent boundary-scan from functioning on the ddr2 memory controller pins. to preserve boundary-scan functionality on the ddr2 memory controller pins, v refsstl , rsv11, and rsv12 should be connected as follows: v refsstl - connect to a voltage of dv dd18 /2. the dv dd18 /2 voltage can be generated directly from the dv dd18 supply using two 1-k w resistors to form a resistor divider circuit. rsv11 - connect this pin to ground (v ss ) via a 200- w resistor. rsv12 - connect this pin to the 1.8-v i/o supply (dv dd18 ) via a 200- w resistor. submit documentation feedback c64x+ peripheral information and electrical specifications 97 product preview www.ti.com
7.4 enhanced direct memory access (edma3) controller 7.4.1 edma3 device-specific information TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the primary purpose of the edma3 is to service user-programmed data transfers between two memory-mapped slave endpoints on the device. the edma3 services software-driven paging transfers (e.g., data movement between external memory and internal memory), performs sorting or subframe extraction of various data structures, services event driven peripherals such as the mcbsp, and offloads data transfers from the device cpu. the edma3 includes the following features: fully orthogonal transfer description ? 3 transfer dimensions: array (multiple bytes), frame (multiple arrays), and block (multiple frames) ? single event can trigger transfer of array, frame, or entire block ? independent indexes on source and destination flexible transfer definition: ? increment or fifo transfer addressing modes ? linking mechanism allows for ping-pong buffering, circular buffering, and repetitive/continuous transfers, all with no cpu intervention ? chaining allows multiple transfers to execute with one event 256 param entries ? used to define transfer context for channels ? each param entry can be used as a dma entry, qdma entry, or link entry 64 dma channels ? manually triggered (cpu writes to channel controller register), external event triggered, and chain triggered (completion of one transfer triggers another) 8 quick dma (qdma) channels ? used for software-driven transfers ? triggered upon writing to a single param set entry 4 transfer controllers/event queues with programmable system-level priority interrupt generation for transfer completion and error conditions memory protection support ? active memory protection for accesses to param and registers debug visibility ? queue watermarking/threshold allows detection of maximum usage of event queues ? error and status recording to facilitate debug each of the transfer controllers has a direct connection to the switched central resource (scr). table 4-1 lists the peripherals that can be accessed by the transfer controllers. a dsp interrupt must be generated at the end of an hpi or pci boot operation to begin execution of the loaded application. since the dsp interrupt generated by the hpi and pci is mapped to the edma event dsp_evt (dma channel 0), it will get recorded in bit 0 of the edma event register (er). this event must be cleared by software before triggering transfers on dma channel 0. the edma3 on the c6454 dsp supports active memory protection, but it does not support proxied memory protection. the edma supports two addressing modes: constant addressing and increment addressing mode. on the c6454 dsp, constant addressing mode is not supported by any peripheral or internal memory. for more information on these two addressing modes, see the tms320c645x dsp enhanced dma (edma) controller user's guide (literature number spru966 ). c64x+ peripheral information and electrical specifications 98 submit documentation feedback www.ti.com product preview
7.4.2 edma3 channel synchronization events TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the edma3 supports up to 64 dma channels that can be used to service system peripherals and to move data between system memories. dma channels can be triggered by synchronization events generated by system peripherals. table 7-3 lists the source of the synchronization event associated with each of the dma channels. on the c6454, the association of each synchronization event and dma channel is fixed and cannot be reprogrammed. for more detailed information on the edma3 module and how edma3 events are enabled, captured, processed, prioritized, linked, chained, and cleared, etc., see the tms320c645x dsp enhanced dma (edma) controller user's guide (literature number spru966 ). table 7-3. c6454 edma3 channel synchronization events (1) edma binary event name event description channel 0 (2) 000 0000 dsp_evt hpi/pci-to-dsp event 1 000 0001 tevtlo0 timer 0 lower counter event 2 000 0010 tevthi0 timer 0 high counter event 3 000 0011 - none 4 000 0100 - none 5 000 0101 - none 6 000 0110 - none 7 000 0111 - none 8 000 1000 - none 9 000 1001 - none 10 000 1010 - none 11 000 1011 - none 12 000 1100 xevt0 mcbsp0 transmit event 13 000 1101 revt0 mcbsp0 receive event 14 000 1110 xevt1 mcbsp1 transmit event 15 000 1111 revt1 mcbsp1 receive event 16 001 0000 tevtlo1 timer 1 lower counter event 17 001 0001 tevthi1 timer 1 high counter event 18-43 - - none 44 010 1100 icrevt i2c receive event 45 010 1101 icxevt i2c transmit event 46-47 - - none 48 011 0000 gpint0 gpio event 0 49 011 0001 gpint1 gpio event 1 50 011 0010 gpint2 gpio event 2 51 011 0011 gpint3 gpio event 3 52 011 0100 gpint4 gpio event 4 53 011 0101 gpint5 gpio event 5 54 011 0110 gpint6 gpio event 6 55 011 0111 gpint7 gpio event 7 56 011 1000 gpint8 gpio event 8 57 011 1001 gpint9 gpio event 9 (1) in addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer completion events. for more detailed information on edma event-transfer chaining, see the tms320c645x dsp enhanced dma (edma) controller user's guide (literature number spru966 ). (2) hpi boot and pci boot are terminated using a dsp interrupt. the dsp interrupt is registered in bit 0 (channel 0) of the edma event register (er). this event must be cleared by software before triggering transfers on dma channel 0. submit documentation feedback c64x+ peripheral information and electrical specifications 99 product preview www.ti.com
7.4.3 edma3 peripheral register description(s) TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-3. c6454 edma3 channel synchronization events (continued) edma binary event name event description channel 58 011 1010 gpint10 gpio event 10 59 011 1011 gpint11 gpio event 11 60 011 1100 gpint12 gpio event 12 61 011 1101 gpint13 gpio event 13 62 011 1110 gpint14 gpio event 14 63 011 1111 gpint15 gpio event 15 table 7-4. edma3 channel controller registers hex address range acronym register name 02a0 0000 pid peripheral id register 02a0 0004 cccfg edma3cc configuration register 02a0 0008 - 02a0 00fc - reserved 02a0 0100 dchmap0 dma channel 0 mapping register 02a0 0104 dchmap1 dma channel 1 mapping register 02a0 0108 dchmap2 dma channel 2 mapping register 02a0 010c dchmap3 dma channel 3 mapping register 02a0 0110 dchmap4 dma channel 4 mapping register 02a0 0114 dchmap5 dma channel 5 mapping register 02a0 0118 dchmap6 dma channel 6 mapping register 02a0 011c dchmap7 dma channel 7 mapping register 02a0 0120 dchmap8 dma channel 8 mapping register 02a0 0124 dchmap9 dma channel 9 mapping register 02a0 0128 dchmap10 dma channel 10 mapping register 02a0 012c dchmap11 dma channel 11 mapping register 02a0 0130 dchmap12 dma channel 12 mapping register 02a0 0134 dchmap13 dma channel 13 mapping register 02a0 0138 dchmap14 dma channel 14 mapping register 02a0 013c dchmap15 dma channel 15 mapping register 02a0 0140 dchmap16 dma channel 16 mapping register 02a0 0144 dchmap17 dma channel 17 mapping register 02a0 0148 dchmap18 dma channel 18 mapping register 02a0 014c dchmap19 dma channel 19 mapping register 02a0 0150 dchmap20 dma channel 20 mapping register 02a0 0154 dchmap21 dma channel 21 mapping register 02a0 0158 dchmap22 dma channel 22 mapping register 02a0 015c dchmap23 dma channel 23 mapping register 02a0 0160 dchmap24 dma channel 24 mapping register 02a0 0164 dchmap25 dma channel 25 mapping register 02a0 0168 dchmap26 dma channel 26 mapping register 02a0 016c dchmap27 dma channel 27 mapping register 02a0 0170 dchmap28 dma channel 28 mapping register 02a0 0174 dchmap29 dma channel 29 mapping register 02a0 0178 dchmap30 dma channel 30 mapping register 02a0 017c dchmap31 dma channel 31 mapping register c64x+ peripheral information and electrical specifications 100 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-4. edma3 channel controller registers (continued) hex address range acronym register name 02a0 0180 dchmap32 dma channel 32 mapping register 02a0 0184 dchmap33 dma channel 33 mapping register 02a0 0188 dchmap34 dma channel 34 mapping register 02a0 018c dchmap35 dma channel 35 mapping register 02a0 0190 dchmap36 dma channel 36 mapping register 02a0 0194 dchmap37 dma channel 37 mapping register 02a0 0198 dchmap38 dma channel 38 mapping register 02a0 019c dchmap39 dma channel 39 mapping register 02a0 01a0 dchmap40 dma channel 40 mapping register 02a0 01a4 dchmap41 dma channel 41 mapping register 02a0 01a8 dchmap42 dma channel 42 mapping register 02a0 01ac dchmap43 dma channel 43 mapping register 02a0 01b0 dchmap44 dma channel 44 mapping register 02a0 01b4 dchmap45 dma channel 45 mapping register 02a0 01b8 dchmap46 dma channel 46 mapping register 02a0 01bc dchmap47 dma channel 47 mapping register 02a0 01c0 dchmap48 dma channel 48 mapping register 02a0 01c4 dchmap49 dma channel 49 mapping register 02a0 01c8 dchmap50 dma channel 50 mapping register 02a0 01cc dchmap51 dma channel 51 mapping register 02a0 01d0 dchmap52 dma channel 52 mapping register 02a0 01d4 dchmap53 dma channel 53 mapping register 02a0 01d8 dchmap54 dma channel 54 mapping register 02a0 01dc dchmap55 dma channel 55 mapping register 02a0 01e0 dchmap56 dma channel 56 mapping register 02a0 01e4 dchmap57 dma channel 57 mapping register 02a0 01e8 dchmap58 dma channel 58 mapping register 02a0 01ec dchmap59 dma channel 59 mapping register 02a0 01f0 dchmap60 dma channel 60 mapping register 02a0 01f4 dchmap61 dma channel 61 mapping register 02a0 01f8 dchmap62 dma channel 62 mapping register 02a0 01fc dchmap63 dma channel 63 mapping register 02a0 0200 qchmap0 qdma channel 0 mapping register 02a0 0204 qchmap1 qdma channel 1 mapping register 02a0 0208 qchmap2 qdma channel 2 mapping register 02a0 020c qchmap3 qdma channel 3 mapping register 02a0 0210 - 02a0 021c - reserved 02a0 0220 - 02a0 023c - reserved 02a0 0240 dmaqnum0 dma queue number register 0 02a0 0244 dmaqnum1 dma queue number register 1 02a0 0248 dmaqnum2 dma queue number register 2 02a0 024c dmaqnum3 dma queue number register 3 02a0 0250 - 02a0 025c - reserved 02a0 0260 qdmaqnum qdma queue number register 02a0 0264 - 02a0 0280 - reserved 02a0 0284 quepri queue priority register 02a0 0288 - 02a0 02fc - reserved submit documentation feedback c64x+ peripheral information and electrical specifications 101 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-4. edma3 channel controller registers (continued) hex address range acronym register name 02a0 0300 emr event missed register 02a0 0304 emrh event missedregister high 02a0 0308 emcr event missed clear register 02a0 030c emcrh event missed clear register high 02a0 0310 qemr qdma event missed register 02a0 0314 qemcr qdma event missed clear register 02a0 0318 ccerr edma3cc error register 02a0 031c ccerrclr edma3cc error clear register 02a0 0320 eeval error evaluate register 02a0 0324 - 02a0 033c - reserved 02a0 0340 drae0 dma region access enable register for region 0 02a0 0344 draeh0 dma region access enable register high for region 0 02a0 0348 drae1 dma region access enable register for region 1 02a0 034c draeh1 dma region access enable register high for region 1 02a0 0350 drae2 dma region access enable register for region 2 02a0 0354 draeh2 dma region access enable register high for region 2 02a0 0358 drae3 dma region access enable register for region 3 02a0 035c draeh3 dma region access enable register high for region 3 02a0 0360 drae4 dma region access enable register for region 4 02a0 0364 draeh4 dma region access enable register high for region 4 02a0 0368 drae5 dma region access enable register for region 5 02a0 036c draeh5 dma region access enable register high for region 5 02a0 0370 drae6 dma region access enable register for region 6 02a0 0374 draeh6 dma region access enable register high for region 6 02a0 0378 drae7 dma region access enable register for region 7 02a0 037c draeh7 dma region access enable register high for region 7 02a0 0380 qrae0 qdma region access enable register for region 0 02a0 0384 qrae1 qdma region access enable register for region 1 02a0 0388 qrae2 qdma region access enable register for region 2 02a0 038c qrae3 qdma region access enable register for region 3 02a0 0390 - 02a0 039c - reserved 02a0 0400 q0e0 event queue 0 entry register 0 02a0 0404 q0e1 event queue 0 entry register 1 02a0 0408 q0e2 event queue 0 entry register 2 02a0 040c q0e3 event queue 0 entry register 3 02a0 0410 q0e4 event queue 0 entry register 4 02a0 0414 q0e5 event queue 0 entry register 5 02a0 0418 q0e6 event queue 0 entry register 6 02a0 041c q0e7 event queue 0 entry register 7 02a0 0420 q0e8 event queue 0 entry register 8 02a0 0424 q0e9 event queue 0 entry register 9 02a0 0428 q0e10 event queue 0 entry register 10 02a0 042c q0e11 event queue 0 entry register 11 02a0 0430 q0e12 event queue 0 entry register 12 02a0 0434 q0e13 event queue 0 entry register 13 02a0 0438 q0e14 event queue 0 entry register 14 02a0 043c q0e15 event queue 0 entry register 15 c64x+ peripheral information and electrical specifications 102 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-4. edma3 channel controller registers (continued) hex address range acronym register name 02a0 0440 q1e0 event queue 1 entry register 0 02a0 0444 q1e1 event queue 1 entry register 1 02a0 0448 q1e2 event queue 1 entry register 2 02a0 044c q1e3 event queue 1 entry register 3 02a0 0450 q1e4 event queue 1 entry register 4 02a0 0454 q1e5 event queue 1 entry register 5 02a0 0458 q1e6 event queue 1 entry register 6 02a0 045c q1e7 event queue 1 entry register 7 02a0 0460 q1e8 event queue 1 entry register 8 02a0 0464 q1e9 event queue 1 entry register 9 02a0 0468 q1e10 event queue 1 entry register 10 02a0 046c q1e11 event queue 1 entry register 11 02a0 0470 q1e12 event queue 1 entry register 12 02a0 0474 q1e13 event queue 1 entry register 13 02a0 0478 q1e14 event queue 1 entry register 14 02a0 047c q1e15 event queue 1 entry register 15 02a0 0480 q2e0 event queue 2 entry register 0 02a0 0484 q2e1 event queue 2 entry register 1 02a0 0488 q2e2 event queue 2 entry register 2 02a0 048c q2e3 event queue 2 entry register 3 02a0 0490 q2e4 event queue 2 entry register 4 02a0 0494 q2e5 event queue 2 entry register 5 02a0 0498 q2e6 event queue 2 entry register 6 02a0 049c q2e7 event queue 2 entry register 7 02a0 04a0 q2e8 event queue 2 entry register 8 02a0 04a4 q2e9 event queue 2 entry register 9 02a0 04a8 q2e10 event queue 2 entry register 10 02a0 04ac q2e11 event queue 2 entry register 11 02a0 04b0 q2e12 event queue 2 entry register 12 02a0 04b4 q2e13 event queue 2 entry register 13 02a0 04b8 q2e14 event queue 2 entry register 14 02a0 04bc q2e15 event queue 2 entry register 15 02a0 04c0 q3e0 event queue 3 entry register 0 02a0 04c4 q3e1 event queue 3 entry register 1 02a0 04c8 q3e2 event queue 3 entry register 2 02a0 04cc q3e3 event queue 3 entry register 3 02a0 04d0 q3e4 event queue 3 entry register 4 02a0 04d4 q3e5 event queue 3 entry register 5 02a0 04d8 q3e6 event queue 3 entry register 6 02a0 04dc q3e7 event queue 3 entry register 7 02a0 04e0 q3e8 event queue 3 entry register 8 02a0 04e4 q3e9 event queue 3 entry register 9 02a0 04e8 q3e10 event queue 3 entry register 10 02a0 04ec q3e11 event queue 3 entry register 11 02a0 04f0 q3e12 event queue 3 entry register 12 02a0 04f4 q3e13 event queue 3 entry register 13 02a0 04f8 q3e14 event queue 3 entry register 14 submit documentation feedback c64x+ peripheral information and electrical specifications 103 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-4. edma3 channel controller registers (continued) hex address range acronym register name 02a0 04fc q3e15 event queue 3 entry register 15 02a0 0500 - 02a0 051c - reserved 02a0 0520 - 02a0 05fc - reserved 02a0 0600 qstat0 queue status register 0 02a0 0604 qstat1 queue status register 1 02a0 0608 qstat2 queue status register 2 02a0 060c qstat3 queue status register 3 02a0 0610 - 02a0 061c - reserved 02a0 0620 qwmthra queue watermark threshold a register 02a0 0624 - 02a0 063c - reserved 02a0 0640 ccstat edma3cc status register 02a0 0644 - 02a0 06fc - reserved 02a0 0700 - 02a0 07fc - reserved 02a0 0800 mpfar memory protection fault address register 02a0 0804 mpfsr memory protection fault status register 02a0 0808 mpfcr memory protection fault command register 02a0 080c mppa0 memory protection page attribute register 0 02a0 0810 mppa1 memory protection page attribute register 1 02a0 0814 mppa2 memory protection page attribute register 2 02a0 0818 mppa3 memory protection page attribute register 3 02a0 081c mppa4 memory protection page attribute register 4 02a0 0820 mppa5 memory protection page attribute register 5 02a0 0824 mppa6 memory protection page attribute register 6 02a0 0828 mppa7 memory protection page attribute register 7 02a0 082c - 02a0 0ffc - reserved 02a0 1000 er event register 02a0 1004 erh event register high 02a0 1008 ecr event clear register 02a0 100c ecrh event clear register high 02a0 1010 esr event set register 02a0 1014 esrh event set register high 02a0 1018 cer chained event register 02a0 101c cerh chained event register high 02a0 1020 eer event enable register 02a0 1024 eerh event enable register high 02a0 1028 eecr event enable clear register 02a0 102c eecrh event enable clear register high 02a0 1030 eesr event enable set register 02a0 1034 eesrh event enable set register high 02a0 1038 ser secondary event register 02a0 103c serh secondary event register high 02a0 1040 secr secondary event clear register 02a0 1044 secrh secondary event clear register high 02a0 1048 - 02a0 104c - reserved 02a0 1050 ier interrupt enable register 02a0 1054 ierh interrupt enable high register 02a0 1058 iecr interrupt enable clear register c64x+ peripheral information and electrical specifications 104 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-4. edma3 channel controller registers (continued) hex address range acronym register name 02a0 105c iecrh interrupt enable clear high register 02a0 1060 iesr interrupt enable set register 02a0 1064 iesrh interrupt enable set high register 02a0 1068 ipr interrupt pending register 02a0 106c iprh interrupt pending high register 02a0 1070 icr interrupt clear register 02a0 1074 icrh interrupt clear high register 02a0 1078 ieval interrupt evaluate register 02a0 107c - reserved 02a0 1080 qer qdma event register 02a0 1084 qeer qdma event enable register 02a0 1088 qeecr qdma event enable clear register 02a0 108c qeesr qdma event enable set register 02a0 1090 qser qdma secondary event register 02a0 1094 qsecr qdma secondary event clear register 02a0 1098 - 02a0 1fff - reserved 02a0 2000 - 02a0 2097 - shadow region 0 channel registers 02a0 2098 - 02a0 21ff - reserved 02a0 2200 - 02a0 2297 - shadow region 1 channel registers 02a0 2298 - 02a0 23ff - reserved 02a0 2400 - 02a0 2497 - shadow region 2 channel registers 02a0 2498 - 02a0 25ff - reserved 02a0 2600 - 02a0 2697 - shadow region 3 channel registers 02a0 2698 - 02a0 27ff - reserved 02a0 2800 - 02a0 2897 - shadow region 4 channel registers 02a0 2898 - 02a0 29ff - reserved 02a0 2a00 - 02a0 2a97 - shadow region 5 channel registers 02a0 2a98 - 02a0 2bff - reserved 02a0 2c00 - 02a0 2c97 - shadow region 6 channel registers 02a0 2c98 - 02a0 2dff - reserved 02a0 2e00 - 02a0 2e97 - shadow region 7 channel registers 02a0 2e98 - 02a0 2fff - reserved table 7-5. edma3 parameter ram (1) hex address range acronym register name 02a0 4000 - 02a0 401f - parameter set 0 02a0 4020 - 02a0 403f - parameter set 1 02a0 4040 - 02a0 405f - parameter set 2 02a0 4060 - 02a0 407f - parameter set 3 02a0 4080 - 02a0 409f - parameter set 4 02a0 40a0 - 02a0 40bf - parameter set 5 02a0 40c0 - 02a0 40df - parameter set 6 02a0 40e0 - 02a0 40ff - parameter set 7 02a0 4100 - 02a0 411f - parameter set 8 02a0 4120 - 02a0 413f - parameter set 9 (1) the c6454 device has 256 edma3 parameter sets total. each parameter set can be used as a dma entry, a qdma entry, or a link entry. submit documentation feedback c64x+ peripheral information and electrical specifications 105 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-5. edma3 parameter ram (continued) hex address range acronym register name ... ... 02a0 47e0 - 02a0 47ff - parameter set 63 02a0 4800 - 02a0 481f - parameter set 64 02a0 4820 - 02a0 483f - parameter set 65 ... ... 02a0 5fc0 - 02a0 5fdf - parameter set 254 02a0 5fe0 - 02a0 5fff - parameter set 255 table 7-6. edma3 transfer controller 0 registers hex address range acronym register name 02a2 0000 pid peripheral identification register 02a2 0004 tccfg edma3tc configuration register 02a2 0008 - 02a2 00fc - reserved 02a2 0100 tcstat edma3tc channel status register 02a2 0104 - 02a2 011c - reserved 02a2 0120 errstat error register 02a2 0124 erren error enable register 02a2 0128 errclr error clear register 02a2 012c errdet error details register 02a2 0130 errcmd error interrupt command register 02a2 0134 - 02a2 013c - reserved 02a2 0140 rdrate read rate register 02a2 0144 - 02a2 023c - reserved 02a2 0240 saopt source active options register 02a2 0244 sasrc source active source address register 02a2 0248 sacnt source active count register 02a2 024c sadst source active destination address register 02a2 0250 sabidx source active source b-index register 02a2 0254 sampprxy source active memory protection proxy register 02a2 0258 sacntrld source active count reload register 02a2 025c sasrcbref source active source address b-reference register 02a2 0260 sadstbref source active destination address b-reference register 02a2 0264 - 02a2 027c - reserved 02a2 0280 dfcntrld destination fifo set count reload 02a2 0284 dfsrcbref destination fifo set destination address b reference register 02a2 0288 dfdstbref destination fifo set destination address b reference register 02a2 028c - 02a2 02fc - reserved 02a2 0300 dfopt0 destination fifo options register 0 02a2 0304 dfsrc0 destination fifo source address register 0 02a2 0308 dfcnt0 destination fifo count register 0 02a2 030c dfdst0 destination fifo destination address register 0 02a2 0310 dfbidx0 destination fifo bidx register 0 02a2 0314 dfmpprxy0 destination fifo memory protection proxy register 0 02a2 0318 - 02a2 033c - reserved 02a2 0340 dfopt1 destination fifo options register 1 02a2 0344 dfsrc1 destination fifo source address register 1 c64x+ peripheral information and electrical specifications 106 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-6. edma3 transfer controller 0 registers (continued) hex address range acronym register name 02a2 0348 dfcnt1 destination fifo count register 1 02a2 034c dfdst1 destination fifo destination address register 1 02a2 0350 dfbidx1 destination fifo bidx register 1 02a2 0354 dfmpprxy1 destination fifo memory protection proxy register 1 02a2 0358 - 02a2 037c - reserved 02a2 0380 dfopt2 destination fifo options register 2 02a2 0384 dfsrc2 destination fifo source address register 2 02a2 0388 dfcnt2 destination fifo count register 2 02a2 038c dfdst2 destination fifo destination address register 2 02a2 0390 dfbidx2 destination fifo bidx register 2 02a2 0394 dfmpprxy2 destination fifo memory protection proxy register 2 02a2 0398 - 02a2 03bc - reserved 02a2 03c0 dfopt3 destination fifo options register 3 02a2 03c4 dfsrc3 destination fifo source address register 3 02a2 03c8 dfcnt3 destination fifo count register 3 02a2 03cc dfdst3 destination fifo destination address register 3 02a2 03d0 dfbidx3 destination fifo bidx register 3 02a2 03d4 dfmpprxy3 destination fifo memory protection proxy register 3 02a2 03d8 - 02a2 7fff - reserved table 7-7. edma3 transfer controller 1 registers hex address range acronym register name 02a2 8000 pid peripheral identification register 02a2 8004 tccfg edma3tc configuration register 02a2 8008 - 02a2 80fc - reserved 02a2 8100 tcstat edma3tc channel status register 02a2 8104 - 02a2 811c - reserved 02a2 8120 errstat error register 02a2 8124 erren error enable register 02a2 8128 errclr error clear register 02a2 812c errdet error details register 02a2 8130 errcmd error interrupt command register 02a2 8134 - 02a2 813c - reserved 02a2 8140 rdrate read rate register 02a2 8144 - 02a2 823c - reserved 02a2 8240 saopt source active options register 02a2 8244 sasrc source active source address register 02a2 8248 sacnt source active count register 02a2 824c sadst source active destination address register 02a2 8250 sabidx source active source b-index register 02a2 8254 sampprxy source active memory protection proxy register 02a2 8258 sacntrld source active count reload register 02a2 825c sasrcbref source active source address b-reference register 02a2 8260 sadstbref source active destination address b-reference register 02a2 8264 - 02a2 827c - reserved 02a2 8280 dfcntrld destination fifo set count reload submit documentation feedback c64x+ peripheral information and electrical specifications 107 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-7. edma3 transfer controller 1 registers (continued) hex address range acronym register name 02a2 8284 dfsrcbref destination fifo set destination address b reference register 02a2 8288 dfdstbref destination fifo set destination address b reference register 02a2 828c - 02a2 82fc - reserved 02a2 8300 dfopt0 destination fifo options register 0 02a2 8304 dfsrc0 destination fifo source address register 0 02a2 8308 dfcnt0 destination fifo count register 0 02a2 830c dfdst0 destination fifo destination address register 0 02a2 8310 dfbidx0 destination fifo bidx register 0 02a2 8314 dfmpprxy0 destination fifo memory protection proxy register 0 02a2 8318 - 02a2 833c - reserved 02a2 8340 dfopt1 destination fifo options register 1 02a2 8344 dfsrc1 destination fifo source address register 1 02a2 8348 dfcnt1 destination fifo count register 1 02a2 834c dfdst1 destination fifo destination address register 1 02a2 8350 dfbidx1 destination fifo bidx register 1 02a2 8354 dfmpprxy1 destination fifo memory protection proxy register 1 02a2 8358 - 02a2 837c - reserved 02a2 8380 dfopt2 destination fifo options register 2 02a2 8384 dfsrc2 destination fifo source address register 2 02a2 8388 dfcnt2 destination fifo count register 2 02a2 838c dfdst2 destination fifo destination address register 2 02a2 8390 dfbidx2 destination fifo bidx register 2 02a2 8394 dfmpprxy2 destination fifo memory protection proxy register 2 02a2 8398 - 02a2 83bc - reserved 02a2 83c0 dfopt3 destination fifo options register 3 02a2 83c4 dfsrc3 destination fifo source address register 3 02a2 83c8 dfcnt3 destination fifo count register 3 02a2 83cc dfdst3 destination fifo destination address register 3 02a2 83d0 dfbidx3 destination fifo bidx register 3 02a2 83d4 dfmpprxy3 destination fifo memory protection proxy register 3 02a2 83d8 - 02a2 ffff - reserved table 7-8. edma3 transfer controller 2 registers hex address range acronym register name 02a3 0000 pid peripheral identification register 02a3 0004 tccfg edma3tc configuration register 02a3 0008 - 02a3 00fc - reserved 02a3 0100 tcstat edma3tc channel status register 02a3 0104 - 02a3 011c - reserved 02a3 0120 errstat error register 02a3 0124 erren error enable register 02a3 0128 errclr error clear register 02a3 012c errdet error details register 02a3 0130 errcmd error interrupt command register 02a3 0134 - 02a3 013c - reserved 02a3 0140 rdrate read rate register c64x+ peripheral information and electrical specifications 108 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-8. edma3 transfer controller 2 registers (continued) hex address range acronym register name 02a3 0144 - 02a3 023c - reserved 02a3 0240 saopt source active options register 02a3 0244 sasrc source active source address register 02a3 0248 sacnt source active count register 02a3 024c sadst source active destination address register 02a3 0250 sabidx source active source b-index register 02a3 0254 sampprxy source active memory protection proxy register 02a3 0258 sacntrld source active count reload register 02a3 025c sasrcbref source active source address b-reference register 02a3 0260 sadstbref source active destination address b-reference register 02a3 0264 - 02a3 027c - reserved 02a3 0280 dfcntrld destination fifo set count reload 02a3 0284 dfsrcbref destination fifo set destination address b reference register 02a3 0288 dfdstbref destination fifo set destination address b reference register 02a3 028c - 02a3 02fc - reserved 02a3 0300 dfopt0 destination fifo options register 0 02a3 0304 dfsrc0 destination fifo source address register 0 02a3 0308 dfcnt0 destination fifo count register 0 02a3 030c dfdst0 destination fifo destination address register 0 02a3 0310 dfbidx0 destination fifo bidx register 0 02a3 0314 dfmpprxy0 destination fifo memory protection proxy register 0 02a3 0318 - 02a3 033c - reserved 02a3 0340 dfopt1 destination fifo options register 1 02a3 0344 dfsrc1 destination fifo source address register 1 02a3 0348 dfcnt1 destination fifo count register 1 02a3 034c dfdst1 destination fifo destination address register 1 02a3 0350 dfbidx1 destination fifo bidx register 1 02a3 0354 dfmpprxy1 destination fifo memory protection proxy register 1 02a3 0358 - 02a3 037c - reserved 02a3 0380 dfopt2 destination fifo options register 2 02a3 0384 dfsrc2 destination fifo source address register 2 02a3 0388 dfcnt2 destination fifo count register 2 02a3 038c dfdst2 destination fifo destination address register 2 02a3 0390 dfbidx2 destination fifo bidx register 2 02a3 0394 dfmpprxy2 destination fifo memory protection proxy register 2 02a3 0398 - 02a3 03bc - reserved 02a3 03c0 dfopt3 destination fifo options register 3 02a3 03c4 dfsrc3 destination fifo source address register 3 02a3 03c8 dfcnt3 destination fifo count register 3 02a3 03cc dfdst3 destination fifo destination address register 3 02a3 03d0 dfbidx3 destination fifo bidx register 3 02a3 03d4 dfmpprxy3 destination fifo memory protection proxy register 3 02a3 03d8 - 02a3 7fff - reserved submit documentation feedback c64x+ peripheral information and electrical specifications 109 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-9. edma3 transfer controller 3 registers hex address range acronym register name 02a3 8000 pid peripheral identification register 02a3 8004 tccfg edma3tc configuration register 02a3 8008 - 02a3 80fc - reserved 02a3 8100 tcstat edma3tc channel status register 02a3 8104 - 02a3 811c - reserved 02a3 8120 errstat error register 02a3 8124 erren error enable register 02a3 8128 errclr error clear register 02a3 812c errdet error details register 02a3 8130 errcmd error interrupt command register 02a3 8134 - 02a3 813c - reserved 02a3 8140 rdrate read rate register 02a3 8144 - 02a3 823c - reserved 02a3 8240 saopt source active options register 02a3 8244 sasrc source active source address register 02a3 8248 sacnt source active count register 02a3 824c sadst source active destination address register 02a3 8250 sabidx source active source b-index register 02a3 8254 sampprxy source active memory protection proxy register 02a3 8258 sacntrld source active count reload register 02a3 825c sasrcbref source active source address b-reference register 02a3 8260 sadstbref source active destination address b-reference register 02a3 8264 - 02a3 827c - reserved 02a3 8280 dfcntrld destination fifo set count reload 02a3 8284 dfsrcbref destination fifo set destination address b reference register 02a3 8288 dfdstbref destination fifo set destination address b reference register 02a3 828c - 02a3 82fc - reserved 02a3 8300 dfopt0 destination fifo options register 0 02a3 8304 dfsrc0 destination fifo source address register 0 02a3 8308 dfcnt0 destination fifo count register 0 02a3 830c dfdst0 destination fifo destination address register 0 02a3 8310 dfbidx0 destination fifo bidx register 0 02a3 8314 dfmpprxy0 destination fifo memory protection proxy register 0 02a3 8318 - 02a3 833c - reserved 02a3 8340 dfopt1 destination fifo options register 1 02a3 8344 dfsrc1 destination fifo source address register 1 02a3 8348 dfcnt1 destination fifo count register 1 02a3 834c dfdst1 destination fifo destination address register 1 02a3 8350 dfbidx1 destination fifo bidx register 1 02a3 8354 dfmpprxy1 destination fifo memory protection proxy register 1 02a3 8358 - 02a3 837c - reserved 02a3 8380 dfopt2 destination fifo options register 2 02a3 8384 dfsrc2 destination fifo source address register 2 02a3 8388 dfcnt2 destination fifo count register 2 02a3 838c dfdst2 destination fifo destination address register 2 02a3 8390 dfbidx2 destination fifo bidx register 2 c64x+ peripheral information and electrical specifications 110 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-9. edma3 transfer controller 3 registers (continued) hex address range acronym register name 02a3 8394 dfmpprxy2 destination fifo memory protection proxy register 2 02a3 8398 - 02a3 83bc - reserved 02a3 83c0 dfopt3 destination fifo options register 3 02a3 83c4 dfsrc3 destination fifo source address register 3 02a3 83c8 dfcnt3 destination fifo count register 3 02a3 83cc dfdst3 destination fifo destination address register 3 02a3 83d0 dfbidx3 destination fifo bidx register 3 02a3 83d4 dfmpprxy3 destination fifo memory protection proxy register 3 02a3 83d8 - 02a3 ffff - reserved submit documentation feedback c64x+ peripheral information and electrical specifications 111 product preview www.ti.com
7.5 interrupts 7.5.1 interrupt sources and interrupt controller TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the cpu interrupts on the c6454 device are configured through the c64x+ megamodule interrupt controller. the interrupt controller allows for up to 128 system events to be programmed to any of the twelve cpu interrupt inputs, the cpu exception input, or the advanced emulation logic. table 8-4 shows the mapping of system events to the interrupt controller inputs. event numbers 0-31 correspond to the default interrupt mapping of the device. the remaining events must be mapped using software. for more information on the interrupt controller, see the tms320c64x+ megamodule reference guide (literature number spru871 ). table 7-10. c6454 dsp interrupts event number interrupt event interrupt source 0 (1) evt0 interrupt controller output of event combiner 0, for events 1 - 31. 1 (1) evt1 interrupt controller output of event combiner 1, for events 32 - 63. 2 (1) evt2 interrupt controller output of event combiner 2, for events 64 - 95. 3 (1) evt3 interrupt controller output of event combiner 3, for events 96 - 127. 4 - 8 (2) reserved reserved. do not use. emu interrupt for: 1. host scan access 9 (2) emu_dtdma 2. dtdma transfer complete 3. aet interrupt 10 (2) reserved reserved. do not use. 11 (2) emu_rtdxrx emu real-time data exchange (rtdx) receive complete 12 (2) emu_rtdxtx emu rtdx transmit complete 13 (2) idma0 idma channel 0 interrupt 14 (2) idma1 idma channel 1 interrupt 15 (2) dspint hpi/pci-to-dsp interrupt 16 i2cint i2c interrupt 17 macint ethernet mac interrupt 18 aeasyncerr emifa error interrupt 19 - 23 reserved reserved. do not use. 24 edma3cc_gint edma3 channel global completion interrupt 25 - 39 reserved reserved. do not use. 40 rint0 mcbsp0 receive interrupt 41 xint0 mcbsp0 transmit interrupt 42 rint1 mcbsp1 receive interrupt 43 xint1 mcbsp1 transmit interrupt 44 - 50 reserved reserved. do not use. 51 gpint0 gpio interrupt 52 gpint1 gpio interrupt 53 gpint2 gpio interrupt 54 gpint3 gpio interrupt 55 gpint4 gpio interrupt 56 gpint5 gpio interrupt 57 gpint6 gpio interrupt 58 gpint7 gpio interrupt (1) interrupts 0 through 3 are non-maskable and fixed. (2) interrupts 4 through 15 are programmable by modifying the binary selector values in the interrupt selector control registers fields. shows the default interrupt sources for interrupts 4 through 15. c64x+ peripheral information and electrical specifications 112 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-10. c6454 dsp interrupts (continued) event number interrupt event interrupt source 59 gpint8 gpio interrupt 60 gpint9 gpio interrupt 61 gpint10 gpio interrupt 62 gpint11 gpio interrupt 63 gpint12 gpio interrupt 64 gpint13 gpio interrupt 65 gpint14 gpio interrupt 66 gpint15 gpio interrupt 67 tintlo0 timer 0 lower counter interrupt 68 tinthi0 timer 0 higher counter interrupt 69 tintlo1 timer 1 lower counter interrupt 70 tinthi1 timer 1 higher counter interrupt 71 edma3cc_int0 edma3cc completion interrupt - mask0 72 edma3cc_int1 edma3cc completion interrupt - mask1 73 edma3cc_int2 edma3cc completion interrupt - mask2 74 edma3cc_int3 edma3cc completion interrupt - mask3 75 edma3cc_int4 edma3cc completion interrupt - mask4 76 edma3cc_int5 edma3cc completion interrupt - mask5 77 edma3cc_int6 edma3cc completion interrupt - mask6 78 edma3cc_int7 edma3cc completion interrupt - mask7 79 edma3cc_errint edma3cc error interrupt 80 reserved reserved. do not use. 81 edma3tc0_errint edma3tc0 error interrupt 82 edma3tc1_errint edma3tc1 error interrupt 83 edma3tc2_errint edma3tc2 error interrupt 84 edma3tc3_errint edma3tc3 error interrupt 85 reserved reserved. do not use. 86 - 95 reserved reserved. do not use. 96 interr interrupt controller dropped cpu interrupt event 97 emc_idmaerr emc invalid idma parameters 98 reserved reserved. do not use. 99 reserved reserved. do not use. 100 efiinta efi interrupt from side a 101 efiintb efi interrupt from side b 102 - 111 reserved reserved. do not use. 112 reserved reserved. do not use. 113 l1p_ed1 l1p single bit error detected during dma read 114 - 115 reserved reserved. do not use. 116 l2_ed1 l2 single bit error detected 117 l2_ed2 l2 two bit error detected 118 pdc_int powerdown sleep interrupt 119 reserved reserved. do not use. 120 l1p_cmpa l1p cpu memory protection fault 121 l1p_dmpa l1p dma memory protection fault 122 l1d_cmpa l1d cpu memory protection fault 123 l1d_dmpa l1d dma memory protection fault 124 l2_cmpa l2 cpu memory protection fault submit documentation feedback c64x+ peripheral information and electrical specifications 113 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-10. c6454 dsp interrupts (continued) event number interrupt event interrupt source 125 l2_dmpa l2 dma memory protection fault 126 idma_cmpa idma cpu memory protection fault 127 idma_buserr idma bus error interrupt c64x+ peripheral information and electrical specifications 114 submit documentation feedback www.ti.com product preview
7.5.2 external interrupts electrical data/timing TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-11. timing requirements for external interrupts (1) (see figure 7-6 ) -720 -850 no. unit -1000 min max 1 t w(nmil) width of the nmi interrupt pulse low 6p ns 2 t w(nmih) width of the nmi interrupt pulse high 6p ns (1) p = 1/cpu clock frequency in ns. for example, when running parts at 1000 mhz, use p = 1 ns. figure 7-6. nmi interrupt timing submit documentation feedback c64x+ peripheral information and electrical specifications 115 product preview www.ti.com 2 1 nmi
7.6 reset controller 7.6.1 power-on reset ( por pin) TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the reset controller detects the different type of resets supported on the c6454 device and manages the distribution of those resets throughout the device. the c6454 device has several types of resets: power-on reset, warm reset, system reset, and cpu reset. table 7-12 explains further the types of reset, the reset initiator, and the effects of each reset on the chip. for more information on the effects of each reset on the pll controllers and their clocks, see section 7.6.7 , reset electrical data/timing. table 7-12. reset types type initiator effect(s) power-on reset por pin resets the entire chip including the test and emulation logic. resets everything except for the test and emulation logic and pll2. warm reset reset pin emulator stays alive during warm reset. a system reset maintains memory contents and does not reset the system reset emulator test and emulation circuitry. the device configuration pins are also not re-latched and the state of the peripherals is also not affected. (1) cpu local reset hpi/pci cpu local reset. (1) on the c6454 device, peripherals can be in one of several states. these states are listed in table 3-4 . power-on reset is initiated by the por pin and is used to reset the entire chip, including the test and emulation logic. power-on reset is also referred to as a cold reset since the device usually goes through a power-up cycle. during power-up, the por pin must be asserted (driven low) until the power supplies have reached their normal operating conditions. note that a device power-up cycle is not required to initiate a power-on reset. the following sequence must be followed during a power-on reset: 1. wait for all power supplies to reach normal operating conditions while keeping the por pin asserted (driven low). while por is asserted, all pins will be set to high-impedance. after the por pin is deasserted (driven high), all z group pins, low group pins, and high group pins are set to their reset state and will remain at their reset state until the otherwise configured by their respective peripheral. all peripherals, except those selected for boot purposes, are disabled after a power-on reset and must be enabled through the device state control registers; for more details, see section 3.3 , peripheral selection after device reset. 2. once all the power supplies are within valid operating conditions, the por pin must remain asserted (low) for a minimum of 256 clkin2 cycles. the pll1 controller input clock, clkin1, and the pci input clock, pclk, must also be valid during this time. pclk is only needed if the pci module is being used. if the ddr2 memory controller and the emac peripheral are not needed, clkin2 can be tied low and, in this case, the por pin must remain asserted (low) for a minimum of 256 clkin1 cycles after all power supplies have reached valid operating conditions. within the low period of the por pin, the following happens: ? the reset signals flow to the entire chip (including the test and emulation logic), resetting modules that use reset asynchronously. ? the pll1 controller clocks are started at the frequency of the system reference clock. the clocks are propagated throughout the chip to reset modules that use reset synchronously. by default, pll1 is in reset and unlocked. ? the pll2 controller clocks are started at the frequency of the system reference clock. pll2 is held in reset. since the pll2 controller always operates in pll mode, the system reference clock and c64x+ peripheral information and electrical specifications 116 submit documentation feedback www.ti.com product preview
7.6.2 warm reset ( reset pin) TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 all the system clocks are invalid at this point. the resetstat pin stays asserted (low), indicating the device is in reset. 3. the por pin may now be deasserted (driven high). when the por pin is deasserted, the configuration pin values are latched and the pll controllers change their system clocks to their default divide-down values. pll2 is taken out of reset and automatically starts its locking sequence. other device initialization is also started. 4. after device initialization is complete, the resetstat pin is deasserted (driven high). by this time, pll2 has already completed its locking sequence and is outputting a valid clock. the system clocks of both pll controllers are allowed to finish their current cycles and then paused for 10 cycles of their respective system reference clocks. after the pause the system clocks are restarted at their default divide-by settings. 5. the device is now out of reset, device execution begins as dictated by the selected boot mode (see section 2.4 , boot sequence). note to most of the device, reset is de-asserted only when the por and reset pins are both de-asserted (driven high). therefore, in the sequence described above, if the reset pin is held low past the low period of the por pin, most of the device will remain in reset. the only exception being that pll2 is taken out of reset as soon as por is de-asserted (driven high), regardless of the state of the reset pin. the reset pin should not be tied together with the por pin. a warm reset has the same effects as a power-on reset, except that in this case, the test and emulation logic and pll2 are not reset. the following sequence must be followed during a warm reset: 1. hold the reset pin low for a minimum of 24 clkin1 cycles. within the minimum 24 clkin1 cycles. within the low period of the reset pin, the following happens: ? the z group pins, low group pins, and the high group pins are set to their reset state with one exception: the pci pins are not affected by warm reset if the pci module was enabled before reset went low. in this case, pci pins stay at whatever their value was before reset went low. ? the reset signals flow to the entire chip (excluding the test and emulation logic), resetting modules that use reset asynchronously. ? the pll1 controller is reset thereby switching back to bypass mode and resetting all its registers to their default values. pll1 is placed in reset and loses lock. the pll1 controller clocks start running at the frequency of the system reference clock. the clocks are propagated throughout the chip to reset modules that use reset synchronously. ? the pll2 controller is reset thereby resetting all its registers to their default values. the pll2 controller clocks start running at the frequency of the system reference clock. pll2 is not reset, therefore it remains locked. ? the resetstat pin becomes active (low), indicating the device is in reset. 2. the reset pin may now be released (driven inactive high). when the reset pin is released, the configuration pin values are latched and the pll controllers immediately change their system clocks to their default divide-down values. other device initialization is also started. 3. after device initialization is complete, the resetstat pin goes inactive (high). all system clocks are allowed to finish their current cycles and then paused for 10 cycles of their respective system reference clocks. after the pause the system clocks are restarted at their default divide-by settings. submit documentation feedback c64x+ peripheral information and electrical specifications 117 product preview www.ti.com
7.6.3 system reset 7.6.4 cpu reset TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 4. the device is now out of reset, device execution begins as dictated by the selected boot mode (see section 2.4 , boot sequence). note the por pin should be held inactive (high) throughout the warm reset sequence. otherwise, if por is activated (brought low), the minimum por pulse width must be met. the reset pin should not be tied together with the por pin. a system reset is initiated by the emulator via the c64x+ emulation logic. this reset can be masked by the emulator. the following memory contents are maintained during a system reset: ddr2 memory controller: the ddr2 memory controller registers are not reset. in addition, the ddr2 sdram memory content is retained if the user places the ddr2 sdram in self-refresh mode before invoking the system reset. emifa: the contents of the memory connected to the emifa are retained. the emifa registers are not reset. test, emulation, and clock logic are unaffected. the device configuration pins are also not re-latched and the state of the peripherals (see table 3-4 ) is not affected. during a system reset, the following happens: 1. the system reset is initiated by the emulator. during this time, the following happens: ? the reset signals flow to the entire chip resetting all the modules on chip except the test and emulation logic. ? the pll controllers are not reset. internal system clocks are unaffected. if pll1/pll2 were locked before the system reset, they remain locked. ? the resetstat pin goes low to indicate an internal reset is being generated. 2. after device initialization is complete, the resetstat pin is deasserted (driven high). in addition, the pll controllers pause their system clocks for about 10 cycles. at this point: ? the state of the peripherals before the system reset is not changed. for example, if mcbsp0 was in the enabled state before system reset, it will remain in the enabled state after system reset. ? the i/o pins are controlled as dictated by the devstat register. ? the ddr2 memory controller and emifa registers retain their previous values. only the ddr2 memory controller and emifa state machines are reset by the system reset. ? the pll controllers are operating in the mode prior to system reset. system clocks are unaffected. the boot sequence is started after the system clocks are restarted. since the configuration pins (including the bootmode[3:0] pins) are not latched with a system reset, the previous values, as shown in the devstat register, are used to select the boot mode. a cpu reset is initiated by the hpi or pci peripheral. this reset only affects the cpu. during a pci-initiated cpu reset, the pci pins are set to their reset state. with the exception of the hrdy/ pirdy pin, the pci pins have a reset state of high-impedance; the hrdy/ pirdy pin goes high during reset. c64x+ peripheral information and electrical specifications 118 submit documentation feedback www.ti.com product preview
7.6.5 reset priority 7.6.6 reset controller register TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 if any of the above reset sources occur simultaneously, the pllctrl only processes the highest priority reset request. the rest request priorities are as follows (high to low): power-on reset maximum reset warm reset system reset cpu reset the reset type status (rstype) register (029a 00e4) is the only register for the reset controller. this register falls in the same memory range as the pll1 controller registers [029a 0000 - 029a 01ff] (see table 7-18 ). 7.6.6.1 reset type status register description the rest type status (rstype) register latches the cause of the last reset. if multiple reset sources occur simultaneously, this register latches the highest priority reset source. the reset type status register is shown in figure 7-7 and described in table 7-13 . 31 16 reserved r-0 15 4 3 2 1 0 reserved srst rsvd wrst por r-0 r-0 r-0 r-0 r-0 legend: r/w = read/write; r = read only; - n = value after reset figure 7-7. reset type status register (rstype) [hex address: 029a 00e4] table 7-13. reset type status register (rstype) field descriptions bit field value description 31:4 reserved reserved. the reserved bit location is always read as 0. a value written to this field has no effect. 3 srst system reset. 0 system reset was not the last reset to occur. 1 system reset was the last reset to occur. 2 reserved reserved. the reserved bit location is always read as 0. a value written to this field has no effect. 1 wrst warm reset. 0 warm reset was not the last reset to occur. 1 warm reset was the last reset to occur. 0 por power-on reset. 0 power-on reset was not the last reset to occur. 1 power-on reset was the last reset to occur. submit documentation feedback c64x+ peripheral information and electrical specifications 119 product preview www.ti.com
7.6.7 reset electrical data/timing TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 note if a configuration pin must be routed out from the device and 3-stated (not driven), the internal pullup/pulldown (ipu/ipd) resistor should not be relied upon; ti recommends the use of an external pullup/pulldown resistor. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.7 , pullup/pulldown resistors. table 7-14. timing requirements for reset (1) (2) (3) (see figure 7-8 and figure 7-9 ) -720 -850 no. unit -1000 min max 5 t w(por) pulse duration, por low 256d (4) ns 6 t w(reset) pulse duration, reset low 24c ns setup time, boot mode and configuration pins valid before por high or 7 t su(boot) 6p ns reset high (5) hold time, boot mode and configuration pins valid after por high or 8 t h(boot) 6p ns reset high (5) (1) c = 1/clkin1 clock frequency in ns. (2) d = 1/clkin2 clock frequency in ns. (3) p = 1/cpu clock frequency in nanoseconds (ns). note that after power-on reset and warm reset the cpu frequency is equal to the clkin1 frequency divided by three due to the pll1 controller being reset (see section 7.6 , reset controller). (4) if clkin2 is not used, t w(por) must be measured in terms of clkin1 cycles; otherwise, use clkin2 cycles. (5) aea[19:0], aba[1:0], and pci_en are the boot configuration pins during device reset. table 7-15. switching characteristics over recommended operating conditions during reset (1) (see figure 7-9 ) -720 -850 no. parameter unit -1000 min max 9 t d(porh-rstath) delay time, por high and reset high to resetstat high 15000c ns (1) c = 1/clkin1 clock frequency in ns. for figure 7-8 , note the following: z group consists of: all i/o/z and o/z pins, except for low and high group pins. pins become high impedance as soon as their respective power supply has reached normal operating coditions. pins remain in high impedance until configured otherwise by their respective peripheral. low group consists of: mtxd0/rmtxd0, mtxd1/rmtxd1, mtxd2/rmtxd2, mtxd3/rmtxd3, mtxd4/rmtxd4, mtxen/rmtxen, and abusreq. pins become low as soon as their respective power supply has reached normal operating conditions. pins remain low until configured otherwise by their respective peripheral. high group consists of: ahold and hrdy/ pirdy. pins become high as soon as their respective power supply has reached normal operating conditions. pins remain high until configured otherwise by their respective peripheral. all peripherals must be enable through software following a power-on reset; for more details, see section 7.6.1 , power-on reset. for power-supply sequence requirements, see section 7.3.1 , power-supply sequencing. c64x+ peripheral information and electrical specifications 120 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 a. sysrefclk of the pll2 controller runs at clkin2 10. b. sysclk1 of pll2 controller runs at sysrefclk/2 (default). c. power supplies, clkin1, clkin2 (if used), and pclk (if used) must be stable before the start of t w(por) . figure 7-8. power-up timing submit documentation feedback c64x+ peripheral information and electrical specifications 121 product preview www.ti.com clkin1 pclk reset resetstat sysrefclk (pll1c) z group por sysclk3 sysclk4 sysclk5 aeclkout (internal) boot and device configuration pins low group high group clkin2 internal reset pll2c sysrefclk (pll2c) sysclk1 (pll2c) sysclk2 5 9 7 8 undefined undefined low high-z undefined high pll2 unlocked pll2 locked (a) pll2 unlocked clock v alid undefinedundefined undefined clock v alid (b) power supplies ramping power supplies stable
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 a. reset should only be used after device has been powered up. for more details on the use of the reset pin, see section 7.6 , reset controller. b. a reset signal is generated internally during a warm reset. this internal reset signal has the same effect as the reset pin during a warm reset. c. boot and device configurations inputs (during reset) include: aea[19:0], aba[1:0], and pci_en. figure 7-9. warm reset timing 122 c64x+ peripheral information and electrical specifications submit documentation feedback www.ti.com product preview clkin1 clkin2 por reset (a)(b) resetstat boot and device configuration pins (c) 9 7 6 8
7.7 pll1 and pll1 controller TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the primary pll controller generates the input clock to the c64x+ megamodule (including the cpu) as well as most of the system peripherals such as the multichannel buffered serial ports (mcbsps) and the external memory interface (emif). as shown in figure 7-10 , the pll1 controller features a software-programmable pll multiplier controller (pllm) and five dividers (prediv, d2, d3, d4, and d5). the pll1 controller uses the device input clock clkin1 to generate a system reference clock (sysrefclk) and four system clocks (sysclk2, sysclk3, sysclk4, and sysclk5). pll1 power is supplied externally via the pll1 power-supply pin (pllv1). an external emi filter circuit must be added to pllv1, as shown in figure 7-10 . the 1.8-v supply of the emi filter must be from the same 1.8-v power plane supplying the i/o power-supply pin, dv dd18 . ti requires emi filter manufacturer murata, part number nfm18cc222r1c3. all pll external components (c1, c2, and the emi filter) must be placed as close to the c64x+ dsp device as possible. for the best performance, ti recommends that all the pll external components be on a single side of the board without jumpers, switches, or components other than the ones shown. for reduced pll jitter, maximize the spacing between switching signals and the pll external components (c1, c2, and the emi filter). the minimum clkin1 rise and fall times should also be observed. for the input clock timing requirements, see section 7.7.4 , pll1 controller input and output clock electrical data/timing. caution the pll controller module as described in the tms320c645x dsp software-programmable phase-locked loop (pll) controller user's guide (literature number sprue56 ) includes a superset of features, some of which are not supported on the c6454 dsp. the following sections describe the features that are supported; it should be assumed that any feature not included in these sections is not supported by the c6454 dsp. submit documentation feedback c64x+ peripheral information and electrical specifications 123 product preview www.ti.com
7.7.1 pll1 controller device-specific information TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 a. divider d2 and divider d3 are always enabled. b. clkin1 is a 3.3-v signal. figure 7-10. pll1 and pll1 controller 7.7.1.1 internal clocks and maximum operating frequencies as shown in figure 7-10 , the pll1 controller generates several internal clocks including the system reference clock (sysrefclk), and the system clocks (sysclk2/3/4/5). the high-frequency clock signal sysrefclk is directly used to clock the c64x+ megamodule (including the cpu) and also serves as a reference clock for the rest of the dsp system. dividers d2, d3, d4, and d5 divide the high-frequency clock sysrefclk to generate sysclk2, sysclk3, sysclk4, and sysclk5, respectively. the system clocks are used to clock different portions of the dsp: sysclk2 is used to clock the switched central resources (scrs), edma3, as well as the data bus interfaces of the emifa and ddr2 memory controller. sysclk3 clocks the pci, hpi, mcbsp, gpio, timer, and i2c peripherals, as well as the configuration bus of the pll2 controller. c64x+ peripheral information and electrical specifications 124 submit documentation feedback www.ti.com product preview 10 0 1 divider d4 clkin1 (b) pllen (pllctl.[0]) sysclk2sysclk3 aeclkin (external emif clock input) emifa divider prediv divider d2 (a) divider d3 (a) aeclkout pllv1 c2 c1 emi filter +1.8 v 560 pf 0.1 f sysclk5(emulation and t race) sysrefclk(c64x+ megamodule) aeclkinsel(aea[15] pin) divider d5 pll1 controller (emif input clock) TMS320C6454 dsp /1, /2, /3 ena preden (prediv .[15]) /3 /6 ena /2, /4,..., /16 ena pll1 pllm x1, x15, x20, x25, x30, x32 d4en (plldiv4.[15]) d5en (plldiv4.[15]) sysclk4(internal emif clock input) /1, /2, ..., /8 1 0 gp1/sysclk4 sysclkout_en(aea[4] pin) gp0 /1, /2, ..., /8 clkdiv(ctrl.[18:16]) pllout pllref
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 sysclk4 is used as the internal clock for the emifa. it is also used to clock other logic within the dsp. sysclk5 clocks the emulation and trace logic of the dsp. the divider ratio bits of dividers d2 and d3 are fixed at 3 and 6, respectively. the divider ratio bits of dividers d4 and 54 are programmable through the pll controller divider registers plldiv4 and plldiv5, respectively. the pll multiplier controller (pllm) and the dividers (d4 and d5) must be programmed after reset. there is no hardware clkmode selection on the c6454 device. since the divider ratio bits for dividers d2 and d3 are fixed, the frequency of sysclk2 and sysclk3 is tied to the frequency of sysrefclk. however, the frequency of sysclk4 and sysclk5 depends on the configuration of dividers d4 and d5. for example, with pllm in the pll1 multiply control register set to 10011b (x20 mode) and a 50 mhz clkin1 input, the pll output pllout is set to 1000 mhz and sysclk2 and sysclk3 run at 333 mhz and 166 mhz, respectively. divider d4 can be programmed through the plldiv4 register to divide sysrefclk by 10 such that sysclk4, and hence the emif internal clock, runs at 100 mhz. all hosts (hpi, pci, etc.) must hold off accesses to the dsp while the frequency of its internal clocks is changing. a mechanism must be in place such that the dsp notifies the host when the pll configuration has completed. note that there is a minimum and maximum operating frequency for pllref, pllout, sysclk4, and sysclk5. the pll1 controller must not be configured to exceed any of these constraints (certain combinations of external clock input, internal dividers, and pll multiply ratios might not be supported). for the pll clocks input and output frequency ranges, see table 7-16 . table 7-16. pll1 clock frequency ranges clock signal min max unit clkin1 66.6 mhz pllref (pllen = 1) (1) 33.3 66.6 mhz pllout (1) 400 1000 mhz sysclk4 25 166 mhz sysclk5 333 mhz (1) only applies when the pll1 controller is set to pll mode (pllen = 1 in the pllctl register). 7.7.1.2 pll1 controller operating modes the pll1 controller has two modes of operation: bypass mode and pll mode. the mode of operation is determined by the pllen bit of the pll control register (pllctl). in pll mode, sysrefclk is generated from the device input clock clkin1 using the divider prediv and the pll multiplier pllm. in bypass mode, clkin1 is fed directly to sysrefclk. all hosts (hpi, pci, etc.) must hold off accesses to the dsp while the frequency of its internal clocks is changing. a mechanism must be in place such that the dsp notifies the host when the pll configuration has completed. 7.7.1.3 pll1 stabilization, lock, and reset times the pll stabilization time is the amount of time that must be allotted for the internal pll regulators to become stable after device powerup. the pll should not be operated until this stabilization time has expired. the pll reset time is the amount of wait time needed when resetting the pll (writing pllrst = 1), in order for the pll to properly reset, before bringing the pll out of reset (writing pllrst = 0). for the pll1 reset time value, see table 7-17 . submit documentation feedback c64x+ peripheral information and electrical specifications 125 product preview www.ti.com
7.7.2 pll1 controller memory map TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the pll lock time is the amount of time needed from when the pll is taken out of reset (pllrst = 1 with pllen = 0) to when to when the pll controller can be switched to pll mode (pllen = 1). the pll1 lock time is given in table 7-17 . table 7-17. pll1 stabilization, lock, and reset times min typ max unit pll stabilization time 150 m s pll lock time 2000*c (1) ns pll reset time 128*c (1) ns (1) c = clkin1 cycle time in ns. for example, when clkin1 frequency is 50 mhz, use c = 20 ns. the memory map of the pll1 controller is shown in table 7-18 . note that only registers documented here are accessible on the TMS320C6454. other addresses in the pll1 controller memory map should not be modified. table 7-18. pll1 controller registers (including reset controller) hex address range acronym register name 029a 0000 - 029a 00e3 - reserved 029a 00e4 rstype reset type status register (reset controller) 029a 00e8 - 029a 00ff - reserved 029a 0100 pllctl pll control register 029a 0104 - reserved 029a 0108 - reserved 029a 010c - reserved 029a 0110 pllm pll multiplier control register 029a 0114 prediv pll pre-divider control register 029a 0118 - reserved 029a 011c - reserved 029a 0120 - reserved 029a 0124 - reserved 029a 0128 - reserved 029a 012c - reserved 029a 0130 - reserved 029a 0134 - reserved 029a 0138 pllcmd pll controller command register 029a 013c pllstat pll controller status register 029a 0140 alnctl pll controller clock align control register 029a 0144 dchange plldiv ratio change status register 029a 0148 - reserved 029a 014c - reserved 029a 0150 systat sysclk status register 029a 0154 - reserved 029a 0158 - reserved 029a 015c - reserved 029a 0160 plldiv4 pll controller divider 4 register 029a 0164 plldiv5 pll controller divider 5 register 029a 0168 - 029b ffff - reserved c64x+ peripheral information and electrical specifications 126 submit documentation feedback www.ti.com product preview
7.7.3 pll1 controller register descriptions TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 this section provides a description of the pll1 controller registers. for details on the operation of the pll controller module, see the tms320c645x dsp software-programmable phase-locked loop (pll) controller user's guide (literature number sprue56 ). note: the pll1 controller registers can only be accessed using the cpu or the emulator. not all of the registers documented in the tms320c645x dsp software-programmable phase-locked loop (pll) controller user's guide (literature number sprue56 ) are supported on the TMS320C6454. only those registers documented in this section are supported. furthermore, only the bits within the registers described here are supported. you should not write to any reserved memory location or change the value of reserved bits. 7.7.3.1 pll1 control register the pll control register (pllctl) is shown in figure 7-11 and described in table 7-19 . 31 16 reserved r-0 15 8 7 6 5 4 3 2 1 0 pll reserved rsvd rsvd reserved pllrst rsvd pllen pwrdn r-0 r/w-0 r-1 r/w-0 r/w-1 r-0 r/w-0 r/w-0 legend: r/w = read/write; r = read only; - n = value after reset figure 7-11. pll1 control register (pllctl) [hex address: 029a 0100] table 7-19. pll1 control register (pllctl) field descriptions bit field value description 31:8 reserved reserved. the reserved bit location is always read as 0. a value written to this field has no effect. 7 reserved reserved. writes to this register must keep this bit as 0. 6 reserved reserved. the reserved bit location is always read as 1. a value written to this field has no effect. 5:4 reserved reserved. writes to this register must keep this bit as 0. 3 pllrst pll reset bit 0 pll reset is released 1 pll reset is asserted 2 reserved reserved. the reserved bit location is always read as 0. a value written to this field has no effect. 1 pllpwrdn pll power-down mode select bit 0 pll is operational 1 pll is placed in power-down state, i.e., all analog circuitry in the pll is turned-off 0 pllen pll enable bit 0 bypass mode. divider prediv and pll are bypassed. all the system clocks (sysclk n) are divided down directly from input reference clock. 1 pll mode. divider prediv and pll are not bypassed. pll output path is enabled. all the system clocks (sysclk n) are divided down from pll output. submit documentation feedback c64x+ peripheral information and electrical specifications 127 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 7.7.3.2 pll multiplier control register the pll multiplier control register (pllm) is shown in figure 7-12 and described in table 7-20 . the pllm register defines the input reference clock frequency multiplier in conjunction with the pll divider ratio bits (ratio) in the pll controller pre-divider register (prediv). 31 16 reserved r-0 15 5 4 0 reserved pllm r-0 r/w-0h legend: r/w = read/write; r = read only; - n = value after reset figure 7-12. pll multiplier control register (pllm) [hex address: 029a 0110] table 7-20. pll multiplier control register (pllm) field descriptions bit field value description 31:5 reserved 0 reserved. the reserved bit location is always read as 0. a value written to this field has no effect. 4:0 pllm pll multiplier bits. defines the frequency multiplier of the input reference clock in conjunction with the pll divider ratio bits (ratio) in prediv. 0h x1 multiplier rate eh x15 multiplier rate 13h x20 multiplier rate 18h x25 multiplier rate 1dh x30 multiplier rate 1fh x32 multiplier rate c64x+ peripheral information and electrical specifications 128 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 7.7.3.3 pll pre-divider control register the pll pre-divider control register (prediv) is shown in figure 7-13 and described in table 7-21 . 31 16 reserved r-0 15 14 5 4 0 preden reserved ratio r/w-1 r-0 r/w-2h legend: r/w = read/write; r = read only; - n = value after reset figure 7-13. pll pre-divider control register (prediv) [hex address: 029a 0114] table 7-21. pll pre-divider control register (prediv) field descriptions bit field value description 31:16 reserved 0 reserved. the reserved bit location is always read as 0. a value written to this field has no effect. 15 preden pre-divider enable bit. 0 pre-divider is disabled. no clock output. 1 pre-divider is enabled. 14:5 reserved 0 reserved. the reserved bit location is always read as 0. a value written to this field has no effect. 4:0 ratio 0-1fh divider ratio bits. 0 1. divide frequency by 1. 1h 2. divide frequency by 2. 2h ? 3. divide frequency by 3. 3h-1fh reserved, do not use. submit documentation feedback c64x+ peripheral information and electrical specifications 129 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 7.7.3.4 pll controller divider 4 register the pll controller divider 4 register (plldiv4) is shown in figure 7-14 and described in table 7-22 . besides being used as the emifa internal clock, sysclk4 is also used in other parts of the system. disabling this clock will cause unpredictable system behavior. therefore, the plldiv4 register should never be used to disable sysclk4. 31 16 reserved r-0 15 14 5 4 0 d4en reserved ratio r/w-1 r-0 r/w-3 legend: r/w = read/write; r = read only; - n = value after reset figure 7-14. pll controller divider 4 register (plldiv4) [hex address: 029a 0160] table 7-22. pll controller divider 4 register (plldiv4) field descriptions bit field value description 31:16 reserved 0 reserved. the reserved bit location is always read as 0. a value written to this field has no effect. 15 d4en divider 4 enable bit. 0 divider 4 is disabled. no clock output. 1 divider 4 is enabled. 14:5 reserved 0 reserved. the reserved bit location is always read as 0. a value written to this field has no effect. 4:0 ratio 0-1fh divider ratio bits. 0 2. divide frequency by 2. 1h 4. divide frequency by 4. 2h 6. divide frequency by 6. 3h 8. divide frequency by 8. 4h-7h 10 to 16. divide frequency by 10 to divide frequency by 16. 8h-1fh reserved, do not use. c64x+ peripheral information and electrical specifications 130 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 7.7.3.5 pll controller divider 5 register the pll controller divider 5 register (plldiv5) is shown in figure 7-15 and described in table 7-23 . 31 16 reserved r-0 15 14 5 4 0 d5en reserved ratio r/w-1 r-0 r/w-3 legend: r/w = read/write; r = read only; - n = value after reset figure 7-15. pll controller divider 5 register (plldiv5) [hex address: 029a 0164] table 7-23. pll controller divider 5 register (plldiv5) field descriptions bit field value description 31:16 reserved 0 reserved. the reserved bit location is always read as 0. a value written to this field has no effect. 15 dn4en divider 4 enable bit. 0 divider 4 is disabled. no clock output. 1 divider 4 is enabled. 14:5 reserved 0 reserved. the reserved bit location is always read as 0. a value written to this field has no effect. 4:0 ratio 0-1fh divider ratio bits. 0 1. divide frequency by 1. 1h 2. divide frequency by 2. 2h 3. divide frequency by 3. 3h 4. divide frequency by 4. 4h-7h 5 to 8. divide frequency by 5 to divide frequency by 8. 8h-1fh reserved, do not use. submit documentation feedback c64x+ peripheral information and electrical specifications 131 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 7.7.3.6 pll controller command register the pll controller command register (pllcmd) contains the command bit for go operation. pllcmd is shown in figure 7-16 and described in table 7-24 . 31 16 reserved r-0 15 2 1 0 reserved rsvd goset r-0 r/w-0 r/w-0 legend: r/w = read/write; r = read only; - n = value after reset figure 7-16. pll controller command register (pllcmd) [hex address: 029a 0138] table 7-24. pll controller command register (pllcmd) field descriptions bit field value description 31:2 reserved 0 reserved. the reserved bit location is always read as 0. a value written to this field has no effect. 1 reserved reserved. the reserved bit location is always read as 0. a value written to this field has no effect. 0 goset go operation command for sysclk rate change and phase alignment. before setting this bit to 1 to initiate a go operation, check the gostat bit in the pllstat register to ensure all previous go operations have completed. 0 no effect. write of 0 clears bit to 0. 1 initiates go operation. write of 1 initiates go operation. once set, goset remains set but further writes of 1 can initiate the go operation. c64x+ peripheral information and electrical specifications 132 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 7.7.3.7 pll controller status register the pll controller status register (pllstat) shows the pll controller status. pllstat is shown in figure 7-17 and described in table 7-25 . 31 16 reserved r-0 15 1 0 reserved gostat r-0 r-0 legend: r/w = read/write; r = read only; - n = value after reset figure 7-17. pll controller status register (pllstat) [hex address: 029a 013c] table 7-25. pll controller status register (pllstat) field descriptions bit field value description 31:1 reserved 0 reserved. the reserved bit location is always read as 0. a value written to this field has no effect. 0 gostat go operation status. 0 go operation is not in progress. sysclk divide ratios are not being changed. 1 go operation is in progress. sysclk divide ratios are being changed. submit documentation feedback c64x+ peripheral information and electrical specifications 133 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 7.7.3.8 pll controller clock align control register the pll controller clock align control register (alnctl) is shown in figure 7-18 and described in table 7-26 . 31 16 reserved r-0 15 5 4 3 2 0 reserved aln5 aln4 reserved r-0 r-1 r-1 r-1 legend: r/w = read/write; r = read only; - n = value after reset figure 7-18. pll controller clock align control register (alnctl) [hex address: 029a 0140] table 7-26. pll controller clock align control register (alnctl) field descriptions bit field value description 31:5 reserved 0 reserved. the reserved bit location is always read as 0. a value written to this field has no effect. 4:3 aln n sysclk n alignment. do not change the default values of these fields. 0 do not align sysclk n to other sysclks during go operation. if sys n in dchange is set to 1, sysclk n switches to the new ratio immediately after the goset bit in pllcmd is set. 1 align sysclk n to other sysclks selected in alnctl when the goset bit in pllcmd is set. the sysclk n ratio is set to the ratio programmed in the ratio bit in plldiv n. 2:0 reserved 0 reserved. the reserved bit location is always read as 0. a value written to this field has no effect. c64x+ peripheral information and electrical specifications 134 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 7.7.3.9 plldiv ratio change status register whenever a different ratio is written to the plldiv n registers, the pllctrl flags the change in the plldiv ratio change status registers (dchange). during the go operation, the pll controller will only change the divide ratio of the sysclks with the bit set in dchange. note that changed clocks will be automatically aligned to other clocks. the plldiv divider ratio change status register is shown in figure 7-19 and described in table 7-27 . 31 16 reserved r-0 15 5 4 3 2 0 reserved sys5 sys4 reserved r-0 r-0 r-0 r-0 legend: r/w = read/write; r = read only; - n = value after reset figure 7-19. plldiv divider ratio change status register (dchange) [hex address: 029a 0144] table 7-27. plldiv divider ratio change status register (dchange) field descriptions bit field value description 31:5 reserved 0 reserved. the reserved bit location is always read as 0. a value written to this field has no effect. 4 sys5 identifies when the sysclk5 divide ratio has been modified. 0 sysclk5 ratio has not been modified. when goset is set, sysclk5 will not be affected. 1 sysclk5 ratio has been modified. when goset is set, sysclk5 will change to the new ratio. 3 sys4 identifies when the sysclk4 divide ratio has been modified. 0 sysclk4 ratio has not been modified. when goset is set, sysclk4 will not be affected. 1 sysclk4 ratio has been modified. when goset is set, sysclk4 will change to the new ratio. 2:0 reserved 0 reserved. the reserved bit location is always read as 0. a value written to this field has no effect. submit documentation feedback c64x+ peripheral information and electrical specifications 135 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 7.7.3.10 sysclk status register the sysclk status register (systat) shows the status of the system clocks (sysclk n). systat is shown in figure 7-20 and described in table 7-28 . 31 16 reserved r-0 15 8 reserved r-0 7 5 4 3 2 1 0 reserved sys5on sys4on sys3on sys2on reserved r-0 r-1 r-1 r-1 r-1 r-1 legend: r = read only; - n = value after reset figure 7-20. sysclk status register (systat) [hex address: 029a 0150] table 7-28. sysclk status register (systat) field descriptions bit field value description 31:4 reserved 0 reserved. the reserved bit location is always read as 0. a value written to this field has no effect. 4:1 sys non sysclk n on status. 0 sysclk n is gated. 1 sysclk n is on. 0 reserved 1 reserved. the reserved bit location is always read as 1. a value written to this field has no effect. c64x+ peripheral information and electrical specifications 136 submit documentation feedback www.ti.com product preview
7.7.4 pll1 controller input and output clock electrical data/timing TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-29. timing requirements for clkin1 devices (1) (2) (3) (see figure 7-21 ) -720 -850 -1000 no. pll modes unit x1 (bypass), x15, x20, x25, x30, x32 min max 1 t c(clkin1) cycle time, clkin1 (4) 15 30.3 ns 2 t w(clkin1h) pulse duration, clkin1 high 0.4c ns 3 t w(clkin1l) pulse duration, clkin1 low 0.4c ns 4 t t(clkin1) transition time, clkin1 1.2 ns 5 t j(clkin1) period jitter (peak-to-peak), clkin1 100 ps (1) the reference points for the rise and fall transitions are measured at 3.3 v v il max and v ih min. (2) for more details on the pll multiplier factors (x1 [bypass], x 15, x20, x25, x30, x32), see section 7.7.1.2 , pll1 controller operating modes. (3) c = clkin1 cycle time in ns. for example, when clkin1 frequency is 50 mhz, use c = 20 ns. (4) the pll1 multiplier factors (x1 [bypass], x 15, x20, x25, x30, x32) further limit the min and max values for t c(clkin1) . for more detailed information on these limitations, see section 7.7.1.1 , internal clocks and maximum operating frequencies. figure 7-21. clkin1 timing table 7-30. switching characteristics over recommended operating conditions for sysclk4 [cpu/8 - cpu/12] (1) (2) (see figure 7-22 ) -720 -850 no. parameter unit -1000 min max 2 t w(cko3h) pulse duration, sysclk4 high 4p ? 0.7 6p + 0.7 ns 3 t w(cko3l) pulse duration, sysclk4 low 4p ? 0.7 6p + 0.7 ns 4 t t(cko3) transition time, sysclk4 1 ns (1) the reference points for the rise and fall transitions are measured at 3.3 v v ol max and v oh min. (2) p = 1/cpu clock frequency in nanoseconds (ns) figure 7-22. sysclk4 timing submit documentation feedback c64x+ peripheral information and electrical specifications 137 product preview www.ti.com clkin1 2 3 4 4 5 1 sysclk4 3 4 4 2
7.8 pll2 and pll2 controller TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the secondary pll controller generates interface clocks for the ethernet media access controller (emac) and the ddr2 memory controller. as shown in figure 7-23 , the pll2 controller features a pll multiplier controller and one divider (d1). the pll multiplier is fixed to a x20 multiplier rate and the divider d1 can be programmed to a 2 or 5 mode. pll2 power is supplied externally via the pll2 power supply (pllv2). an external pll filter circuit must be added to pllv2 as shown in figure 7-23 . the 1.8-v supply for the emi filter must be from the same 1.8-v power plane supplying the i/o power-supply pin, dv dd18 . ti requires emi filter manufacturer murata, part number nfm18cc222r1c3. all pll external components (c161, c162, and the emi filter) should be placed as close to the c64x+ dsp device as possible. for the best performance, ti requires that all the pll external components be on a single side of the board without jumpers, switches, or components other than the ones shown. for reduced pll jitter, maximize the spacing between switching signals and the pll external components (c161, c162, and the emi filter). the minimum clkin2 rise and fall times should also be observed. for the input clock timing requirements, see section 7.8.4 , pll2 controller input clock electrical data/timing. caution the pll controller module as described in the tms320c645x dsp software-programmable phase-locked loop (pll) controller user's guide (literature number sprue56 ) includes a superset of features, some of which are not supported on the c6454 dsp. the following sections describe the features that are supported; it should be assumed that any feature not included in these sections is not supported by the c6454 dsp. a. /x must be programmed to /2 for gmii (default) and to /5 for rgmii. b. if emac is enabled with rgmii, or gmii, clkin2 frequency must be 25 mhz. c. clkin2 is a 3.3-v signal. figure 7-23. pll2 block diagram 138 c64x+ peripheral information and electrical specifications submit documentation feedback www.ti.com product preview pllv2 pll2 sysclk2 (from pll1 controller) sysclk1 ddr2 memory controller emac clkin2 (b)(c) c162 560 pf emi filter +1.8 v c161 0.1 pf pll2 controller TMS320C6454 dsp pllm x20 /2 10 /x (a) 1 sysrefclk sysclk3 (from pll1 controller) pllref pllout divider d1
7.8.1 pll2 controller device-specific information TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 7.8.1.1 internal clocks and maximum operating frequencies as shown in figure 7-23 , the output of pll2, pllout, is divided by 2 and directly fed to the ddr2 memory controller. this clock is used by the ddr2 memory controller to generate ddr2clkout and ddr2clkout. note that, internally, the data bus interface of the ddr2 memory controller is clocked by sysclk2 of the pll1 controller. the pllout/2 clock is also fed back into the pll2 controller where it becomes sysrefclk. divider d1 of the pll2 controller generates sysclk1 for the ethernet media access controller (emac). the emac uses sysclk1 to generate the necessary clock for each of its interfaces. divider d1 should be programmed to 2 mode [default] when using the gigabit media independent interface (gmii) mode and to 5 mode when using the reduce gigabit media independent interface (rgmii). divider d1 is software programmable and, if necessary, must be programmed after device reset to 5 when the rgmii mode of the emac is used. note that, internally, the data bus interface of the emac is clocked by sysclk3 of the pll2 controller. note that there is a minimum and maximum operating frequency for pllref, pllout, and sysclk1. the clock generator must not be configured to exceed any of these constraints. for the pll clocks input and output frequency ranges, see table 7-31 . also, when emac is enabled with rgmii or gmii, clkin2 must be 25 mhz. table 7-31. pll2 clock frequency ranges clock signal min max unit pllref (pllen = 1) 12.5 26.7 mhz pllout 250 533 mhz sysclk1 (1) 50 125 mhz (1) sysclk1 restriction applies only when the emac is enabled and the rgmii or gmii modes are used. sysclk1 must be programmed to 125 mhz when the gmii mode is used and to 50 mhz when the rgmii mode is used. 7.8.1.2 pll2 controller operating modes unlike the pll1 controller which can operate in bypass and a pll mode, the pll2 controller only operates in pll mode. in this mode, sysrefclk is generated outside the pll2 controller by dividing the output of pll2 by two. the pll2 controller is affected by power-on reset and warm reset. during these resets the pll2 controller registers get reset to their default values. the internal clocks of the pll2 controller are also affected as described in section 7.6 , reset controller. pll2 is only unlocked during the power-up sequence (see section 7.6 , reset controller ) and is locked by the time the resetstat pin goes high. it does not lose lock during any of the other resets. submit documentation feedback c64x+ peripheral information and electrical specifications 139 product preview www.ti.com
7.8.2 pll2 controller memory map 7.8.3 pll2 controller register descriptions TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the memory map of the pll2 controller is shown in table 7-32 . note that only registers documented here are accessible on the TMS320C6454. other addresses in the pll2 controller memory map should not be modified. table 7-32. pll2 controller registers hex address range acronym description 029c 0000 - 029c 0114 - reserved 029c 0118 plldiv1 pll controller divider 1 register 029c 011c - 029c 0134 - reserved 029c 0138 pllcmd pll controller command register 029c 013c pllstat pll controller status register 029c 0140 alnctl pll controller clock align control register 029c 0144 dchange plldiv ratio change status register 029c 0148 - reserved 029c 014c - reserved 029c 0150 systat sysclk status register 029c 0154 - 029c 0190 - reserved 029c 0194 - 029c 01ff - reserved 029c 0200 - 029c ffff - reserved this section provides a description of the pll2 controller registers. for details on the operation of the pll controller module, see the tms320c645x dsp software-programmable phase-locked loop (pll) controller user's guide (literature number sprue56 ). note: the pll2 controller registers can only be accessed using the cpu or the emulator. not all of the registers documented in the tms320c645x dsp software-programmable phase-locked loop (pll) controller user's guide (literature number sprue56 ) are supported on the TMS320C6454. only those registers documented in this section are supported. furthermore, only the bits within the registers described here are supported. you should not write to any reserved memory location or change the value of reserved bits. 140 c64x+ peripheral information and electrical specifications submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 7.8.3.1 pll controller divider 1 register the pll controller divider 1 register (plldiv1) is shown in figure 7-24 and described in table 7-33 . 31 16 reserved r-0 15 14 5 4 0 d1en reserved ratio r/w-1 r-0 r/w-1 legend: r/w = read/write; r = read only; - n = value after reset figure 7-24. pll controller divider 1 register (plldiv1) [hex address: 029c 0118] table 7-33. pll controller divider 1 register (plldiv1) field descriptions bit field value description 31:16 reserved 0 reserved. the reserved bit location is always read as 0. a value written to this field has no effect. 15 d1en divider d1 enable bit. 0 divider d1 is disabled. no clock output. 1 divider d1 is enabled. 14:5 reserved 0 reserved. the reserved bit location is always read as 0. a value written to this field has no effect. 4:0 ratio 0-1fh divider ratio bits. 1h 2. divide frequency by 2. 4h 5. divide frequency by 5. others reserved submit documentation feedback c64x+ peripheral information and electrical specifications 141 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 7.8.3.2 pll controller command register the pll controller command register (pllcmd) contains the command bit for go operation. pllcmd is shown in figure 7-25 and described in table 7-34 . 31 16 reserved r-0 15 2 1 0 reserved rsvd goset r-0 r/w-0 r/w-0 legend: r/w = read/write; r = read only; - n = value after reset figure 7-25. pll controller command register (pllcmd) [hex address: 029c 0138] table 7-34. pll controller command register (pllcmd) field descriptions bit field value description 31:2 reserved 0 reserved. the reserved bit location is always read as 0. a value written to this field has no effect. 1 reserved reserved. the reserved bit location is always read as 0. a value written to this field has no effect. 0 goset go operation command for sysclk rate change and phase alignment. before setting this bit to 1 to initiate a go operation, check the gostat bit in the pllstat register to ensure all previous go operations have completed. 0 no effect. write of 0 clears bit to 0. 1 initiates go operation. write of 1 initiates go operation. once set, goset remains set but further writes of 1 can initiate the go operation. c64x+ peripheral information and electrical specifications 142 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 7.8.3.3 pll controller status register the pll controller status register (pllstat) shows the pll controller status. pllstat is shown in figure 7-26 and described in table 7-35 . 31 16 reserved r-0 15 1 0 reserved gostat r-0 r-0 legend: r/w = read/write; r = read only; - n = value after reset figure 7-26. pll controller status register (pllstat) [hex address: 029c 013c] table 7-35. pll controller status register (pllstat) field descriptions bit field value description 31:1 reserved 0 reserved. the reserved bit location is always read as 0. a value written to this field has no effect. 0 gostat go operation status. 0 go operation is not in progress. sysclk divide ratios are not being changed. 1 go operation is in progress. sysclk divide ratios are being changed. 7.8.3.4 pll controller clock align control register the pll controller clock align control register (alnctl) is shown in figure 7-18 and described in table 7-26 . 31 16 reserved r-0 15 1 0 reserved aln1 r-0 r/w-1 legend: r/w = read/write; r = read only; - n = value after reset figure 7-27. pll controller clock align control register (alnctl) [hex address: 029c 0140] table 7-36. pll controller clock align control register (alnctl) field descriptions bit field value description 31:1 reserved 0 reserved. the reserved bit location is always read as 0. a value written to this field has no effect. 0 aln1 sysclk1 alignment. do not change the default values of these fields. 0 do not align sysclk1 during go operation. if sys1 in dchange is set to 1, sysclk1 switches to the new ratio immediately after the goset bit in pllcmd is set. 1 align sysclk1 when the goset bit in pllcmd is set. the sysclk1 ratio is set to the ratio programmed in the ratio bit in plldiv1. submit documentation feedback c64x+ peripheral information and electrical specifications 143 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 7.8.3.5 plldiv ratio change status register whenever a different ratio is written to the plldiv1 register, the pllctrl flags the change in the dchange status register. during the go operation, the pll controller will only change the divide ratio sysclk1 if sys1 in dchange is 1. the plldiv divider ratio change status register is shown in figure 7-28 and described in table 7-37 . 31 16 reserved r-0 15 1 0 reserved sys1 r-0 r-0 legend: r/w = read/write; r = read only; - n = value after reset figure 7-28. plldiv divider ratio change status register (dchange) [hex address: 029c 0144] table 7-37. plldiv divider ratio change status register (dchange) field descriptions bit field value description 31:1 reserved 0 reserved. the reserved bit location is always read as 0. a value written to this field has no effect. 0 sys1 sysclk1 divide ratio has been modified. sysclk1 ratio will be modified during go operation. 0 sysclk1 ratio has not been modified. when goset is set, sysclk1 will not be affected. 1 sysclk1 ratio has been modified. when goset is set, sysclk1 will change to the new ratio. c64x+ peripheral information and electrical specifications 144 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 7.8.3.6 sysclk status register the sysclk status register (systat) shows the status of the system clock (sysclk1). systat is shown in figure 7-29 and described in table 7-38 . 31 16 reserved r-0 15 1 0 reserved sys1on r-0 r-1 legend: r/w = read/write; r = read only; - n = value after reset figure 7-29. sysclk status register [hex address: 029c 0150] table 7-38. sysclk status register field descriptions bit field value description 31:1 reserved 0 reserved. the reserved bit location is always read as 0. a value written to this field has no effect. 0 sys1on sysclk1 on status. 0 sysclk1 is gated. 1 sysclk1 is on. submit documentation feedback c64x+ peripheral information and electrical specifications 145 product preview www.ti.com
7.8.4 pll2 controller input clock electrical data/timing TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-39. timing requirements for clkin2 (1) (2) (3) (see figure 7-30 ) -720 -850 no. unit -1000 min max 1 t c(clkin2) cycle time, clkin2 37.5 80 ns 2 t w(clkin2h) pulse duration, clkin2 high 0.4c ns 3 t w(clkin2l) pulse duration, clkin2 low 0.4c ns 4 t t(clkin2) transition time, clkin2 1.2 ns 5 t j(clkin2) period jitter (peak-to-peak), clkin2 100 ps (1) the reference points for the rise and fall transitions are measured at 3.3 v v il max and v ih min. (2) c = clkin2 cycle time in ns. for example, when clkin2 frequency is 25 mhz, use c = 40 ns. (3) if emac is enabled with rgmii or gmii, clkin2 cycle time must be 40 ns (25 mhz). figure 7-30. clkin2 timing 146 c64x+ peripheral information and electrical specifications submit documentation feedback www.ti.com product preview clkin2 2 3 4 4 5 1
7.9 ddr2 memory controller 7.9.1 ddr2 memory controller device-specific information TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the 32-bit ddr2 memory controller bus of the c6454 is used to interface to jesd79d-2a standard-compliant ddr2 sdram devices. the ddr2 external bus only interfaces to ddr2 sdram devices; it does not share the bus with any other types of peripherals. the decoupling of ddr2 memories from other devices both simplifies board design and provides i/o concurrency from a second external memory interface, emifa. the internal data bus clock frequency and ddr2 bus clock frequency directly affect the maximum throughput of the ddr2 bus. the clock frequency of the ddr2 bus is equal to the clkin2 frequency multiplied by 10. the internal data bus clock frequency of the ddr2 memory controller is fixed at a divide-by-three ratio of the cpu frequency. the maximum ddr2 throughput is determined by the smaller of the two bus frequencies. for example, if the internal data bus frequency is 333 mhz (cpu frequency is 1 ghz) and the ddr2 bus frequency is 250 mhz (clkin2 frequency is 25 mhz), the maximum data rate achievable by the ddr2 memory controller is 2.0 gbytes/sec. the ddr2 bus is designed to sustain a maximum throughput of up to 2.0 gbytes/sec at a 533-mhz data rate (250-mhz clock rate), as long as data requests are pending in the ddr2 memory controller. the approach to specifying interface timing for the ddr2 memory bus is different than on other interfaces such as emif, hpi, and mcbsp. for these other interfaces the device timing was specified in terms of data manual specifications and i/o buffer information specification (ibis) models. for the c6454 ddr2 memory bus, the approach is to specify compatible ddr2 devices and provide the printed circuit board (pcb) solution and guidelines directly to the user. texas instruments (ti) has performed the simulation and system characterization to ensure all ddr2 interface timings in this solution are met. the complete ddr2 system solution is documented in the implementing ddr2 pcb layout on the TMS320C6454 application report (literature number spraaa7 ). ti only supports designs that follow the board design guidelines outlined in the spraaa7 application report. the ddr2 memory controller pins must be enabled by setting the ddr2_en configuration pin (aba0) high during device reset. for more details, see section 3.1 , device configuration at device reset. the odt[1:0] pins of the memory controller must be left unconnected. the odt pins on the ddr2 memory device(s) must be connected to ground. the ddr2 memory controller on the c6454 device supports the following memory topologies: a 32-bit wide configuration interfacing to two 16-bit wide ddr2 sdram devices. a 16-bit wide configuration interfacing to a single 16-bit wide ddr2 sdram device. a race condition may exist when certain masters write data to the ddr2 memory controller. for example, if master a passes a software message via a buffer in external memory and does not wait for indication that the write completes, when master b attempts to read the software message, then the master b read may bypass the master a write and, thus, master b may read stale data and, therefore, receive an incorrect message. some master peripherals (e.g., edma3 transfer controllers) will always wait for the write to complete before signaling an interrupt to the system, thus avoiding this race condition. for masters that do not have hardware guarantee of write-read ordering, it may be necessary to guarantee data ordering via software. if master a does not wait for indication that a write is complete, it must perform the following workaround: 1. perform the required write. 2. perform a dummy write to the ddr2 memory controller module id and revision register. 3. perform a dummy read to the ddr2 memory controller module id and revision register. 4. indicate to master b that the data is ready to be read after completion of the read in step 3. the completion of the read in step 3 ensures that the previous write was done. submit documentation feedback c64x+ peripheral information and electrical specifications 147 product preview www.ti.com
7.9.2 ddr2 memory controller peripheral register description(s) 7.9.3 ddr2 memory controller electrical data/timing TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-40. ddr2 memory controller registers hex address range acronym register name 7800 0000 midr ddr2 memory controller module and revision register 7800 0004 dmcstat ddr2 memory controller status register 7800 0008 sdcfg ddr2 memory controller sdram configuration register 7800 000c sdrfc ddr2 memory controller sdram refresh control register 7800 0010 sdtim1 ddr2 memory controller sdram timing 1 register 7800 0014 sdtim2 ddr2 memory controller sdram timing 2 register 7800 0018 - reserved 7800 0020 bprio ddr2 memory controller burst priority register 7800 0024 - 7800 004c - reserved 7800 0050 - 7800 0078 - reserved 7800 007c - 7800 00bc - reserved 7800 00c0 - 7800 00e0 - reserved 7800 00e4 dmcctl ddr2 memory controller control register 7800 00e8 - 7800 00fc - reserved 7800 0100 - 7fff ffff - reserved the implementing ddr2 pcb layout on the TMS320C6454 application report (literature number spraaa7 ) specifies a complete ddr2 interface solution for the c6454 as well as a list of compatible ddr2 devices. ti has performed the simulation and system characterization to ensure all ddr2 interface timings in this solution are met; therefore, no electrical data/timing information is supplied here for this interface. ti only supports designs that follow the board design guidelines outlined in the spraaa7 application report. 148 c64x+ peripheral information and electrical specifications submit documentation feedback www.ti.com product preview
7.10 external memory interface a (emifa) 7.10.1 emifa device-specific information TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the emifa can interface to a variety of external devices or asics, including: pipelined and flow-through synchronous-burst sram (sbsram) zbt (zero bus turnaround) sram and late write sram synchronous fifos asynchronous memory, including sram, rom, and flash timing analysis must be done to verify all ac timings are met. ti recommends utilizing i/o buffer information specification (ibis) to analyze all ac timings. to properly use ibis models to attain accurate timing analysis for a given system, see the using ibis models for timing analysis application report (literature number spra839 ). to maintain signal integrity, serial termination resistors should be inserted into all emif output signal lines (for the emif output signals, see table 2-3 , terminal functions). a race condition may exist when certain masters write data to the emifa. for example, if master a passes a software message via a buffer in external memory and does not wait for indication that the write completes, when master b attempts to read the software message, then the master b read may bypass the master a write and, thus, master b may read stale data and, therefore, receive an incorrect message. some master peripherals (e.g., edma3 transfer controllers) will always wait for the write to complete before signaling an interrupt to the system, thus avoiding this race condition. for masters that do not have hardware guarantee of write-read ordering, it may be necessary to guarantee data ordering via software. if master a does not wait for indication that a write is complete, it must perform the following workaround: 1. perform the required write. 2. perform a dummy write to the emifa module id and revision register. 3. perform a dummy read to the emifa module id and revision register. 4. indicate to master b that the data is ready to be read after completion of the read in step 3. the completion of the read in step 3 ensures that the previous write was done. submit documentation feedback c64x+ peripheral information and electrical specifications 149 product preview www.ti.com
7.10.2 emifa peripheral register description(s) TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-41. emifa registers hex address range acronym register name 7000 0000 midr module id and revision register 7000 0004 stat status register 7000 0008 - reserved 7000 000c - 7000 001c - reserved 7000 0020 burst_prio burst priority register 7000 0024 - 7000 004c - reserved 7000 0050 - 7000 007c - reserved 7000 0080 ce2cfg emifa ce2 configuration register 7000 0084 ce3cfg emifa ce3 configuration register 7000 0088 ce4cfg emifa ce4 configuration register 7000 008c ce5cfg emifa ce5 configuration register 7000 0090 - 7000 009c - reserved 7000 00a0 awcc emifa async wait cycle configuration register 7000 00a4 - 7000 00bc - reserved 7000 00c0 intraw emifa interrupt raw register 7000 00c4 intmsk emifa interrupt masked register 7000 00c8 intmskset emifa interrupt mask set register 7000 00cc intmskclr emifa interrupt mask clear register 7000 00d0 - 7000 00dc - reserved 7000 00e0 - 77ff ffff - reserved c64x+ peripheral information and electrical specifications 150 submit documentation feedback www.ti.com product preview
7.10.3 emifa electrical data/timing TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-42. timing requirements for aeclkin for emifa (1) (2) (see figure 7-31 ) -720 -850 no. unit -1000 min max 1 t c(eki) cycle time, aeclkin 6 (3) 40 ns 2 t w(ekih) pulse duration, aeclkin high 2.7 ns 3 t w(ekil) pulse duration, aeclkin low 2.7 ns 4 t t(eki) transition time, aeclkin 2 ns 5 t j(eki) period jitter, aeclkin 0.02e (4) ns (1) the reference points for the rise and fall transitions are measured at v il max and v ih min. (2) e = the emif input clock (aeclkin or sysclk4) period in ns for emifa. (3) minimum aeclkin cycle times must be met, even when aeclkin is generated by an internal clock source. minimum aeclkin times are based on internal logic speed; the maximum useable speed of the emif may be lower due to ac timing requirements. (4) this timing only applies when aeclkin is used for emifa. figure 7-31. aeclkin timing for emifa submit documentation feedback c64x+ peripheral information and electrical specifications 151 product preview www.ti.com aeclkin 2 3 4 4 5 1
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-43. switching characteristics over recommended operating conditions for aeclkout for the emifa module (1) (2) (3) (see figure 7-32 ) -720 -850 no. parameter unit -1000 min max 1 t c(eko) cycle time, aeclkout e ? 0.7 e + 0.7 ns 2 t w(ekoh) pulse duration, aeclkout high eh ? 0.7 eh + 0.7 ns 3 t w(ekol) pulse duration, aeclkout low el ? 0.7 el + 0.7 ns 4 t t(eko) transition time, aeclkout 1 ns 5 t d(ekih-ekoh) delay time, aeclkin high to aeclkout high 1 8 ns 6 t d(ekil-ekol) delay time, aeclkin low to aeclkout low 1 8 ns (1) e = the emif input clock (aeclkin or sysclk4) period in ns for emifa. (2) the reference points for the rise and fall transitions are measured at v ol max and v oh min. (3) eh is the high period of e (emif input clock period) in ns and el is the low period of e (emif input clock period) in ns for emifa. figure 7-32. aeclkout timing for the emifa module 7.10.3.1 asynchronous memory timing table 7-44. timing requirements for asynchronous memory cycles for emifa module (1) (2) (3) (see figure 7-33 and figure 7-34 ) -720 -850 no. unit -1000 min max 3 t su(edv-aoeh) setup time, aedx valid before aaoe high 6.5 ns 4 t h(aoeh-edv) hold time, aedx valid after aaoe high 3 ns 5 t su(ardy-ekoh) setup time, aardy valid before aeclkout low 1 ns 6 t h(ekoh-ardy) hold time, aardy valid after aeclkout low 2 ns 7 t w(ardy) pulse width, aardy assertion and deassertion 2e + 5 ns delay time, from aardy sampled deasserted on aeclkout falling to 8 t d(ardy-hold) 4e ns beginning of programmed hold period setup time, before end of programmed strobe period by which aardy 9 t su(ardy-hold) 2e ns should be asserted in order to insert extended strobe wait states. (1) e = aeclkout period in ns for emifa (2) to ensure data setup time, simply program the strobe width wide enough. (3) aardy is internally synchronized. to use aardy as an asynchronous input, the pulse width of the aardy signal should be at least 2e to ensure setup and hold time is met. c64x+ peripheral information and electrical specifications 152 submit documentation feedback www.ti.com product preview 4 5 1 2 aeclkin aeclkout1 3 3
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-45. switching characteristics over recommended operating conditions for asynchronous memory cycles for emifa module (1) (2) (3) (see figure 7-33 and figure 7-34 ) -720 -850 no. parameter unit -1000 min max 1 t osu(selv-aoel) output setup time, select signals valid to aaoe low rs * e ? 1.5 ns 2 t oh(aoeh-seliv) output hold time, aaoe high to select signals invalid rs * e ? 1.9 ns 10 t d(ekoh-aoev) delay time, aeclkout high to aaoe valid 1 7 ns 11 t osu(selv-awel) output setup time, select signals valid to aawe low ws * e ? 1.7 ns 12 t oh(aweh-seliv) output hold time, aawe high to select signals invalid wh * e ? 1.8 ns 13 t d(ekoh-awev) delay time, aeclkout high to aawe valid 1.3 7.1 ns (1) e = aeclkout period in ns for emifa (2) rs = read setup, rst = read strobe, rh = read hold, ws = write setup, wst = write strobe, wh = write hold. these parameters are programmed via the emifa ce configuration registers (cencfg). (3) select signals for emifa include: acex, abe[7:0], aea[19:0], aba[1:0]; and for emifa writes, also include ar/ w, aed[63:0]. figure 7-33. asynchronous memory read timing for emifa submit documentation feedback c64x+ peripheral information and electrical specifications 153 product preview www.ti.com aeclkout acex abe[7:0] aea[19:0]/ aba[1:0] aed[63:0] aaoe /asoe (a) ar/w aawe /aswe (a) aardy (b) byte enables address read data hold = 1 2 strobe = 4 setup = 1 2 2 4 10 10 1 1 1 3 a aaoe /asoe and aa we /aswe operate as aaoe (identified under select signals) and aa we , respectively , during asynchronous memory accesses. b polarity of the aardy signal is programmable through the ap field of the emif a async w ait cycle configuration register (a wcc). deasserted
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 figure 7-34. asynchronous memory write timing for emifa figure 7-35. aardy timing 154 c64x+ peripheral information and electrical specifications submit documentation feedback www.ti.com product preview aeclkout acex abe[7:0] aea[19:0]/ aba[1:0] aed[63:0] aaoe /asoe (a) ar/w aawe /aswe (a) aardy (b) byte enables address w rite data hold = 1 12 strobe = 4 setup = 1 12 12 12 12 13 13 11 11 11 11 11 a aaoe /asoe and aa we /aswe operate as aaoe (identified under select signals) and aa we , respectively , during asynchronous memory accesses. b polarity of the aardy signal is programmable through the ap field of the emif a async w ait cycle configuration register (a wcc). deasserted aeclkout aardy (a) asserted deasserted strobe hold = 2 extended strobe strobe setup = 2 a polarity of the aardy signal is programmable through the ap field of the emif a async w ait cycle configuration register (a wcc). 8 9 6 5 7 7
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 7.10.3.2 programmable synchronous interface timing table 7-46. timing requirements for programmable synchronous interface cycles for emifa module (see figure 7-36 ) -720 -850 no. unit -1000 min max 6 t su(edv-ekoh) setup time, read aedx valid before aeclkout high 2 ns 7 t h(ekoh-edv) hold time, read aedx valid after aeclkout high 1.5 ns table 7-47. switching characteristics over recommended operating conditions for programmable synchronous interface cycles for emifa module (1) (see figure 7-36 ?figure 7-38 ) -720 -850 no. parameter unit -1000 min max 1 t d(ekoh-cev) delay time, aeclkout high to acex valid 1.3 4.9 ns 2 t d(ekoh-bev) delay time, aeclkout high to abex valid 4.9 ns 3 t d(ekoh-beiv) delay time, aeclkout high to abex invalid 1.3 ns 4 t d(ekoh-eav) delay time, aeclkout high to aeax valid 4.9 ns 5 t d(ekoh-eaiv) delay time, aeclkout high to aeax invalid 1.3 ns 8 t d(ekoh-adsv) delay time, aeclkout high to asads/ asre valid 1.3 4.9 ns 9 t d(ekoh-oev) delay time, aeclkout high to asoe valid 1.3 4.9 ns 10 t d(ekoh-edv) delay time, aeclkout high to aedx valid 4.9 ns 11 t d(ekoh-ediv) delay time, aeclkout high to aedx invalid 1.3 ns 12 t d(ekoh-wev) delay time, aeclkout high to aswe valid 1.3 4.9 ns (1) the following parameters are programmable via the emifa ce configuration registers (cencfg): read latency (r_ltncy): 0-, 1-, 2-, or 3-cycle read latency write latency (w_ltncy): 0-, 1-, 2-, or 3-cycle write latency acex assertion length (ce_ext): for standard sbsram or zbt sram interface, acex goes inactive after the final command has been issued (ce_ext = 0). for synchronous fifo interface with glue, acex is active when asoe is active (ce_ext = 1). function of asads/ asre (r_enable): for standard sbsram or zbt sram interface, asads/ asre acts as asads with deselect cycles (r_enable = 0). for fifo interface, asads/ asre acts as asre with no deselect cycles (r_enable = 1). submit documentation feedback c64x+ peripheral information and electrical specifications 155 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 figure 7-36. programmable synchronous interface read timing for emifa (with read latency = 2) (a) figure 7-37. programmable synchronous interface write timing for emifa (with write latency = 0) (a) c64x+ peripheral information and electrical specifications 156 submit documentation feedback www.ti.com product preview aeclkout acex abe[7:0] aea[19:0]/aba[1:0] aed[63:0] asads /asre (b) aaoe /asoe (b) aawe /aswe (b) be1 be2 be3 be4 q1 q2 q3 9 1 4 5 8 9 6 7 3 1 2 be1 be2 be3 be4 ea1 ea2 ea4 8 read latency = 2 ea3 a the following parameters are programmable via the emif a chip select n configuration register (cesecn): ? read latency (r_l tncy): 1-, 2-, or 3-cycle read latency ?w rite latency (w_l tncy): 0-, 1-, 2-, or 3-cycle read latency ?acex assertion length (ce_ext): for standard sbsram or zbt sram interface, acex goes inactive after the final command has been issued (ce_ext = 0). for synchronous fifo interface, acex is active when asoe is active (ce_ext = 1). ?function of asads /asre (r_enable): for standard sbsram or zbt sram interface, asads /asre acts as asads with deselect cycles (r_enable = 0). for fifo interface, asads /asre acts as sre with no deselect cycles (r_enable = 1). ? in this figure r_l tncy = 2, ce_ext = 0, r_enable = 0, and ssel = 1. b aaoe /asoe , and aa we /aswe operate as asoe , and aswe , respectively , during programmable synchronous interface accesses. q4 aeclkout acex abe[7:0] aea[19:0]/aba[1:0] aed[63:0] asads /asre (b) aaoe /asoe (b) aawe /aswe (b) be1 be2 be3 be4 q1 q2 q3 q4 12 11 3 1 12 10 4 2 1 8 5 8 ea1 ea2 ea3 ea4 10 a the following parameters are programmable via the emif a chip select n configuration register (cesecn): ? read latency (r_l tncy): 1-, 2-, or 3-cycle read latency ? w rite latency (w_l tncy): 0-, 1-, 2-, or 3-cycle read latency ? acex assertion length (ce_ext): for standard sbsram or zbt sram interface, acex goes inactive after the final command has been issued (ce_ext = 0). for synchronous fifo interface, acex is active when asoe is active (ce_ext = 1). ? function of asads /asre (r_enable): for standard sbsram or zbt sram interface, asads /asre acts as asads with deselect cycles (r_enable = 0). for fifo interface, asads /asre acts as sre with no deselect cycles (r_enable = 1). ? in this figure w_l tncy = 0, ce_ext = 0, r_enable = 0, and ssel = 1. b aaoe /asoe , and aa we /aswe operate as asoe , and aswe , respectively , during programmable synchronous interface accesses.
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 figure 7-38. programmable synchronous interface write timing for emifa (with write latency = 1) (a) submit documentation feedback c64x+ peripheral information and electrical specifications 157 product preview www.ti.com aeclkout acex abe[7:0] aea[19:0]/aba[1:0] aed[63:0] asads /asre (b) aaoe /asoe (b) aawe /aswe (b) be1 be2 be3 be4 q1 q2 q3 11 3 12 10 4 2 1 8 5 8 ea1 ea2 ea3 ea4 10 write latency = 1 (b) 1 q4 12 a the following parameters are programmable via the emif a chip select n configuration register (cesecn): ? read latency (r_l tncy): 1-, 2-, or 3-cycle read latency ? w rite latency (w_l tncy): 0-, 1-, 2-, or 3-cycle read latency ? acex assertion length (ce_ext): for standard sbsram or zbt sram interface, acex goes inactive after the final command has been issued (ce_ext = 0). for synchronous fifo interface, acex is active when asoe is active (ce_ext = 1). ? function of asads /asre (r_enable): for standard sbsram or zbt sram interface, asads /asre acts as asads with deselect cycles (r_enable = 0). for fifo interface, asads /asre acts as sre with no deselect cycles (r_enable = 1). ? in this figure w_l tncy = 1, ce_ext = 0, r_enable = 0, and ssel = 1. b aaoe /asoe , and aa we /aswe operate as asoe , and aswe , respectively , during programmable synchronous interface accesses.
7.10.4 hold/ holda timing TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-48. timing requirements for the hold/ holda cycles for emifa module (1) (see figure 7-39 ) -720 -850 no. unit -1000 min max 3 t h(holdal-holdl) hold time, hold low after holda low e ns (1) e = the emif input clock (eclkin) period in ns for emifa. table 7-49. switching characteristics over recommended operating conditions for the hold/ holda cycles for emifa module (1) (2) (see figure 7-39 ) -720 -850 no. parameter unit -1000 min max 1 t d(holdl-emhz) delay time, hold low to emifa bus high impedance 2e (3) ns 2 t d(emhz-holdal) delay time, emif bus high impedance to holda low 0 2e ns 4 t d(holdh-emlz) delay time, hold high to emif bus low impedance 2e 7e ns 5 t d(emlz-holdah) delay time, emifa bus low impedance to holda high 0 2e ns (1) e = the emif input clock (eclkin) period in ns for emifa. (2) emifa bus consists of: ace[5:2], abe[7:0], aed[63:0], aea[19:0], aba[1:0], ar/ w, asads/ asre, aaoe/ asoe, and aawe/ aswe. (3) all pending emif transactions are allowed to complete before holda is asserted. if no bus transactions are occurring, then the minimum delay time can be achieved. a. emifa bus consists of: ace[5:2], abe[7:0], aed[63:0], aea[19:0], aba[1:0], ar/ w, asads/ asre, aaoe/ asoe, and aawe/ aswe. figure 7-39. hold/ holda timing for emifa 158 c64x+ peripheral information and electrical specifications submit documentation feedback www.ti.com product preview hold holda emif bus (a) dsp owns bus external requestor owns bus dsp owns bus dsp dsp 1 3 2 5 4 aeclkout
7.10.5 busreq timing TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-50. switching characteristics over recommended operating conditions for the busreq cycles for emifa module (see figure 7-40 ) -720 -850 no. parameter unit -1000 min max 1 t d(aekoh-abusrv) delay time, aeclkout high to abusreq valid 1 5.5 ns figure 7-40. busreq timing for emifa submit documentation feedback c64x+ peripheral information and electrical specifications 159 product preview www.ti.com aeclkoutx 1 abusreq 1
7.11 i2c peripheral 7.11.1 i2c device-specific information TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the inter-integrated circuit (i2c) module provides an interface between a c64x+ dsp and other devices compliant with philips semiconductors inter-ic bus (i 2 c bus) specification version 2.1 and connected by way of an i 2 c-bus. external components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the dsp through the i2c module. the c6454 device includes an i2c peripheral module (i2c). note: when using the i2c module, ensure there are external pullup resistors on the sda and scl pins. the i2c modules on the c6454 may be used by the dsp to control local peripherals ics (dacs, adcs, etc.) or may be used to communicate with other controllers in a system or to implement a user interface. the i2c port supports: compatible with philips i2c specification revision 2.1 (january 2000) fast mode up to 400 kbps (no fail-safe i/o buffers) noise filter to remove noise 50 ns or less 7- and 10-bit device addressing modes multi-master (transmit/receive) and slave (transmit/receive) functionality events: dma, interrupt, or polling slew-rate limited open-drain output buffers figure 7-41 is a block diagram of the i2c module. c64x+ peripheral information and electrical specifications 160 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 figure 7-41. i2c module block diagram submit documentation feedback c64x+ peripheral information and electrical specifications 161 product preview www.ti.com clock prescale i2cpsc peripheral clock(cpu/6) i2cclkh generator bit clock i2cclkl noise filter scl i2cxsr i2cdxr transmit transmit shift transmit buffer i2cdrr shift i2crsr receivebuffer receive receive filter sda i2c data noise i2coar i2csar slaveaddress control address own i2cmdr i2ccnt modedata count vector interrupt interruptstatus i2civr i2cstr mask/status interrupt i2cimr interrupt/dma i2c module i2c clock shading denotes control/status registers. i2cemdr extendedmode
7.11.2 i2c peripheral register description(s) TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-51. i2c registers hex address range acronym register name 02b0 4000 icoar i2c own address register 02b0 4004 icimr i2c interrupt mask/status register 02b0 4008 icstr i2c interrupt status register 02b0 400c icclkl i2c clock low-time divider register 02b0 4010 icclkh i2c clock high-time divider register 02b0 4014 iccnt i2c data count register 02b0 4018 icdrr i2c data receive register 02b0 401c icsar i2c slave address register 02b0 4020 icdxr i2c data transmit register 02b0 4024 icmdr i2c mode register 02b0 4028 icivr i2c interrupt vector register 02b0 402c icemdr i2c extended mode register 02b0 4030 icpsc i2c prescaler register 02b0 4034 icpid1 i2c peripheral identification register 1 [value: 0x0000 0105] 02b0 4038 icpid2 i2c peripheral identification register 2 [value: 0x0000 0005] 02b0 403c - 02b0 405c - reserved 02b0 4060 - 02b3 407f - reserved 02b0 4080 - 02b3 ffff - reserved c64x+ peripheral information and electrical specifications 162 submit documentation feedback www.ti.com product preview
7.11.3 i2c electrical data/timing TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 7.11.3.1 inter-integrated circuits (i2c) timing table 7-52. timing requirements for i2c timings (1) (see figure 7-42 ) -720 -850 -1000 no. unit standard mode fast mode min max min max 1 t c(scl) cycle time, scl 10 2.5 m s setup time, scl high before sda low (for a 2 t su(sclh-sdal) 4.7 0.6 m s repeated start condition) hold time, scl low after sda low (for a 3 t h(scll-sdal) 4 0.6 m s start and a repeated start condition) 4 t w(scll) pulse duration, scl low 4.7 1.3 m s 5 t w(sclh) pulse duration, scl high 4 0.6 m s 6 t su(sdav-sdlh) setup time, sda valid before scl high 250 100 (2) ns hold time, sda valid after scl low (for i 2 c 7 t h(sda-sdll) 0 (3) 0 (3) 0.9 (4) m s bus? devices) pulse duration, sda high between stop and 8 t w(sdah) start 4.7 1.3 m s conditions 9 t r(sda) rise time, sda 1000 20 + 0.1c b (5) 300 ns 10 t r(scl) rise time, scl 1000 20 + 0.1c b (5) 300 ns 11 t f(sda) fall time, sda 300 20 + 0.1c b (5) 300 ns 12 t f(scl) fall time, scl 300 20 + 0.1c b (5) 300 ns setup time, scl high before sda high (for 13 t su(sclh-sdah) 4 0.6 m s stop condition) 14 t w(sp) pulse duration, spike (must be suppressed) 0 50 ns 15 c b (5) capacitive load for each bus line 400 400 pf (1) the i2c pins sda and scl do not feature fail-safe i/o buffers. these pins could potentially draw current when the device is powered down. (2) a fast-mode i 2 c-bus? device can be used in a standard-mode i 2 c-bus? system, but the requirement t su(sda-sclh) 3 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max + t su(sda-sclh) = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. (3) a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. (4) the maximum t h(sda-scll) has only to be met if the device does not stretch the low period [t w(scll) ] of the scl signal. (5) c b = total capacitance of one bus line in pf. if mixed with hs-mode devices, faster fall-times are allowed. submit documentation feedback c64x+ peripheral information and electrical specifications 163 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 figure 7-42. i2c receive timings table 7-53. switching characteristics for i2c timings (1) (see figure 7-43 ) -720 -850 -1000 no. parameter unit standard mode fast mode min max min max 16 t c(scl) cycle time, scl 10 2.5 m s delay time, scl high to sda low (for a 17 t d(sclh-sdal) 4.7 0.6 m s repeated start condition) delay time, sda low to scl low (for a start 18 t d(sdal-scll) 4 0.6 m s and a repeated start condition) 19 t w(scll) pulse duration, scl low 4.7 1.3 m s 20 t w(sclh) pulse duration, scl high 4 0.6 m s 21 t d(sdav-sdlh) delay time, sda valid to scl high 250 100 ns valid time, sda valid after scl low (for i 2 c 22 t v(sdll-sdav) 0 0 0.9 m s bus? devices) pulse duration, sda high between stop and 23 t w(sdah) 4.7 1.3 m s start conditions 24 t r(sda) rise time, sda 1000 20 + 0.1c b (1) 300 ns 25 t r(scl) rise time, scl 1000 20 + 0.1c b (1) 300 ns 26 t f(sda) fall time, sda 300 20 + 0.1c b (1) 300 ns 27 t f(scl) fall time, scl 300 20 + 0.1c b (1) 300 ns delay time, scl high to sda high (for stop 28 t d(sclh-sdah) 4 0.6 m s condition) 29 c p capacitance for each i2c pin 10 10 pf (1) c b = total capacitance of one bus line in pf. if mixed with hs-mode devices, faster fall-times are allowed. c64x+ peripheral information and electrical specifications 164 submit documentation feedback www.ti.com product preview 10 8 4 3 7 12 5 6 14 2 3 13 stop start repeated start stop sda scl 1 11 9
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 figure 7-43. i2c transmit timings submit documentation feedback c64x+ peripheral information and electrical specifications 165 product preview www.ti.com 25 23 19 18 22 27 20 21 17 18 28 stop start repeated start stop sda scl 16 26 24
7.12 host-port interface (hpi) peripheral 7.12.1 hpi device-specific information 7.12.2 hpi peripheral register description(s) TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the c6454 device includes a user-configurable 16-bit or 32-bit host-port interface (hpi16/hpi32). the aea14 pin controls the hpi_width, allowing the user to configure the hpi as a 16-bit or 32-bit peripheral. software handshaking via the hrdy bit of the host port control register (hpic) is not supported on the c6454. an hpi boot is terminated using a dsp interrupt. the dsp interrupt is registered in bit 0 (channel 0) of the edma event register (er). this event must be cleared by software before triggering transfers on dma channel 0. table 7-54. hpi control registers hex address range acronym register name comments 0288 0000 - reserved pwremu_mgmt has both 0288 0004 pwremu_mgmt hpi power and emulation management register host/cpu read/write access. 0288 0008 - 0288 0024 - reserved 0288 0028 - reserved 0288 002c - reserved the host and the cpu have 0288 0030 hpic hpi control register read/write access to the hpic register. (1) hpia hpi address register the host has read/write 0288 0034 (hpiaw) (2) (write) access to the hpia registers. the cpu has only read hpia hpi address register 0288 0038 access to the hpia registers. (hpiar) (2) (read) 0288 000c - 028b 007f - reserved 0288 0080 - 028b ffff - reserved (1) the cpu can write 1 to the hint bit to generate an interrupt to the host and it can write 1 to the dspint bit to clear/acknowledge an interrupt from the host. (2) there are two 32-bit hpia registers: hpiar for read operations and hpiaw for write operations. the hpi can be configured such that hpiar and hpiaw act as a single 32-bit hpia (single-hpia mode) or as two separate 32-bit hpias (dual-hpia mode) from the perspective of the host. the cpu can access hpiaw and hpiar independently. for details about the hpia registers and their modes, see the tms320c645x dsp host port interface (hpi) user's guide (literature number spru969 ). 166 c64x+ peripheral information and electrical specifications submit documentation feedback www.ti.com product preview
7.12.3 hpi electrical data/timing TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-55. timing requirements for host-port interface cycles (1) (2) (see table 7-56 through figure 7-51 ) -720 -850 no. unit -1000 min max 9 t su(hasl-hstbl) setup time, has low before hstrobe low 5 ns 10 t h(hstbl-hasl) hold time, has low after hstrobe low 2 ns 11 t su(selv-hasl) setup time, select signals (3) valid before has low 5 ns 12 t h(hasl-selv) hold time, select signals (3) valid after has low 5 ns 13 t w(hstbl) pulse duration, hstrobe low 15 ns 14 t w(hstbh) pulse duration, hstrobe high between consecutive accesses 2m ns 15 t su(selv-hstbl) setup time, select signals (3) valid before hstrobe low 5 ns 16 t h(hstbl-selv) hold time, select signals (3) valid after hstrobe low 5 ns 17 t su(hdv-hstbh) setup time, host data valid before hstrobe high 5 ns 18 t h(hstbh-hdv) hold time, host data valid after hstrobe high 1 ns 37 t su(hcsl-hstbl) setup time, hcs low before hstrobe low 0 ns hold time, hstrobe low after hrdy low. hstrobe should not be 38 t h(hrdyl-hstbl) inactivated until hrdy is active (low); otherwise, hpi writes will not 1.1 ns complete properly. (1) hstrobe refers to the following logical operation on hcs, hds1, and hds2: [not( hds1 xor hds2)] or hcs. (2) m = sysclk3 period = 6/cpu clock frequency in ns. for example, when running parts at 1000 mhz, use m = 6 ns. (3) select signals include: hcntl[1:0] and hr/ w. for hpi16 mode only, select signals also include hhwil. submit documentation feedback c64x+ peripheral information and electrical specifications 167 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-56. switching characteristics for host-port interface cycles (1) (2) (see table 7-56 through figure 7-51 ) -720 -850 no. parameter unit -1000 min max case 1. hpic or hpia read 5 15 case 2. hpid read with no 9 * m + 20 auto-increment (3) delay time, hstrobe low to case 3. hpid read with auto-increment 1 t d(hstbl-hdv) ns 9 * m + 20 dsp data valid and read fifo initially empty (3) case 4. hpid read with auto-increment and data previously prefetched into the 5 15 read fifo 2 t dis(hstbh-hdv) disable time, hd high-impedance from hstrobe high 1 4 ns 3 t en(hstbl-hd) enable time, hd driven from hstrobe low 3 15 ns 4 t d(hstbl-hrdyh) delay time, hstrobe low to hrdy high 12 ns 5 t d(hstbh-hrdyh) delay time, hstrobe high to hrdy high 12 ns case 1. hpid read with no 10 * m + 20 auto-increment (3) delay time, hstrobe low to 6 t d(hstbl-hrdyl) ns hrdy low case 2. hpid read with auto-increment 10 * m + 20 and read fifo initially empty (3) 7 t d(hdv-hrdyl) delay time, hd valid to hrdy low 0 ns case 1. hpia write (3) 5 * m + 20 delay time, hstrobe high to 34 t d(dsh-hrdyl) ns case 2. hpid write with no hrdy low 5 * m + 20 auto-increment (3) delay time, hstrobe low to hrdy low for hpia write and fifo not 35 t d(hstbl-hrdyl) 40 * m + 20 ns empty (3) 36 t d(hasl-hrdyh) delay time, has low to hrdy high 12 ns (1) m = sysclk3 period = 6/cpu clock frequency in ns. for example, when running parts at 1000 mhz, use m = 6 ns. (2) hstrobe refers to the following logical operation on hcs, hds1, and hds2: [not( hds1 xor hds2)] or hcs. (3) assumes the hpi is accessing l2/l1 memory and no other master is accessing the same memory location. c64x+ peripheral information and electrical specifications 168 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 a. hstrobe refers to the following logical operation on hcs, hds1, and hds2: [not( hds1 xor hds2)] or hcs. b. depending on the type of write or read operation (hpid without auto-incrementing; hpia, hpic, or hpid with auto-incrementing) and the state of the fifo, transitions on hrdy may or may not occur. for more detailed information on the hpi peripheral, see the tms320c645x dsp host port interface (hpi) user's guide (literature number spru969 ). figure 7-44. hpi16 read timing ( has not used, tied high) submit documentation feedback c64x+ peripheral information and electrical specifications 169 product preview www.ti.com hcs has hcntl[1:0] hr/w hhwil hstrobe (a) hd[15:0] hrdy (b) 16 15 37 13 14 16 15 37 13 3 1 2 3 1 2 38 7 4 6
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 a. hstrobe refers to the following logical operation on hcs, hds1, and hds2: [not( hds1 xor hds2)] or hcs. b. depending on the type of write or read operation (hpid without auto-incrementing; hpia, hpic, or hpid with auto-incrementing) and the state of the fifo, transitions on hrdy may or may not occur. for more detailed information on the hpi peripheral, see the tms320c645x dsp host port interface (hpi) user's guide (literature number spru969 ). figure 7-45. hpi16 read timing ( has used) c64x+ peripheral information and electrical specifications 170 submit documentation feedback www.ti.com product preview hcs has hr/w hhwil hstrobe (a) hd[15:0] hrdy (b) 2 3 1 37 9 10 14 2 38 12 11 12 11 12 11 13 7 6 1 3 13 37 9 10 36 hcntl[1:0] 12 11 12 11 12 11
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 a. hstrobe refers to the following logical operation on hcs, hds1, and hds2: [not( hds1 xor hds2)] or hcs. b. depending on the type of write or read operation (hpid without auto-incrementing; hpia, hpic, or hpid with auto-incrementing) and the state of the fifo, transitions on hrdy may or may not occur. for more detailed information on the hpi peripheral, see the tms320c645x dsp host port interface (hpi) user's guide (literature number spru969 ). figure 7-46. hpi16 write timing ( has not used, tied high) submit documentation feedback c64x+ peripheral information and electrical specifications 171 product preview www.ti.com hcs has hcntl[1:0] hr/w hhwil hstrobe (a) hd[15:0] hrdy (b) 34 5 17 18 17 18 34 5 4 38 37 13 16 15 14 13 16 15 37 35
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 a. hstrobe refers to the following logical operation on hcs, hds1, and hds2: [not( hds1 xor hds2)] or hcs. b. depending on the type of write or read operation (hpid without auto-incrementing; hpia, hpic, or hpid with auto-incrementing) and the state of the fifo, transitions on hrdy may or may not occur. for more detailed information on the hpi peripheral, see the tms320c645x dsp host port interface (hpi) user's guide (literature number spru969 ). figure 7-47. hpi16 write timing ( has used) c64x+ peripheral information and electrical specifications 172 submit documentation feedback www.ti.com product preview hcs has hcntl[1:0] hr/w hhwil hstrobe (a) hd[15:0] hrdy (b) 5 34 17 18 13 10 12 9 37 12 12 11 11 11 17 18 14 11 11 11 37 10 9 13 12 12 12 5 34 38 35 36
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 a. hstrobe refers to the following logical operation on hcs, hds1, and hds2: [not( hds1 xor hds2)] or hcs. b. depending on the type of write or read operation (hpid without auto-incrementing; hpia, hpic, or hpid with auto-incrementing) and the state of the fifo, transitions on hrdy may or may not occur. for more detailed information on the hpi peripheral, see the tms320c645x dsp host port interface (hpi) user's guide (literature number spru969 ). figure 7-48. hpi32 read timing ( has not used, tied high) submit documentation feedback c64x+ peripheral information and electrical specifications 173 product preview www.ti.com 15 16 3 2 4 1 38 13 7 6 hcs (input) has (input) hstrobe (a) (input) hr/w (input) hrdy (b) (output) hd[31:0] (output) hcntl[1:0] (input) 37
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 a. hstrobe refers to the following logical operation on hcs, hds1, and hds2: [not( hds1 xor hds2)] or hcs. b. depending on the type of write or read operation (hpid without auto-incrementing; hpia, hpic, or hpid with auto-incrementing) and the state of the fifo, transitions on hrdy may or may not occur. for more detailed information on the hpi peripheral, see the tms320c645x dsp host port interface (hpi) user's guide (literature number spru969 ). figure 7-49. hpi32 read timing ( has used) c64x+ peripheral information and electrical specifications 174 submit documentation feedback www.ti.com product preview 36 11 10 12 9 1 38 13 2 3 6 hcs (input) has (input) hstrobe (a) (input) hr/w (input) hrdy (b) (output) hd[31:0] (output) hcntl[1:0] (input) 7 37
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 a. hstrobe refers to the following logical operation on hcs, hds1, and hds2: [not( hds1 xor hds2)] or hcs. b. depending on the type of write or read operation (hpid without auto-incrementing; hpia, hpic, or hpid with auto-incrementing) and the state of the fifo, transitions on hrdy may or may not occur. for more detailed information on the hpi peripheral, see the tms320c645x dsp host port interface (hpi) user's guide (literature number spru969 ). figure 7-50. hpi32 write timing ( has not used, tied high) submit documentation feedback c64x+ peripheral information and electrical specifications 175 product preview www.ti.com 17 15 38 5 16 13 18 34 35 4 hcs (input) has (input) hstrobe (a) (input) hr/w (input) hrdy (b) (output) hd[31:0] (input) hcntl[1:0] (input) 37
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 a. hstrobe refers to the following logical operation on hcs, hds1, and hds2: [not( hds1 xor hds2)] or hcs. b. depending on the type of write or read operation (hpid without auto-incrementing; hpia, hpic, or hpid with auto-incrementing) and the state of the fifo, transitions on hrdy may or may not occur. for more detailed information on the hpi peripheral, see the tms320c645x dsp host port interface (hpi) user's guide (literature number spru969 ). figure 7-51. hpi32 write timing ( has used) 176 c64x+ peripheral information and electrical specifications submit documentation feedback www.ti.com product preview hrdy (b) (output) 5 11 9 17 18 34 has (input) hr/w (input) hstrobe (a) (input) hcs (input) 35 36 38 hd[31:0] (input) hcntl[1:0] (input) 10 12 13 37
7.13 multichannel buffered serial port (mcbsp) TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the mcbsp provides these functions: full-duplex communication double-buffered data registers, which allow a continuous data stream independent framing and clocking for receive and transmit direct interface to industry-standard codecs, analog interface chips (aics), and other serially connected analog-to-digital (a/d) and digital-to-analog (d/a) devices external shift clock or an internal, programmable frequency shift clock for data transfer for more detailed information on the mcbsp peripheral, see the tms320c6000 dsp multichannel buffered serial port ( mcbsp) reference guide (literature number spru580, rev. e or later). submit documentation feedback c64x+ peripheral information and electrical specifications 177 product preview www.ti.com
7.13.1 mcbsp device-specific information TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the clks signal is shared by both mcbsp0 and mcbsp1 on this device. also, the clkgdv field of the sample rate generator register (srgr) must always be set to a value of 1 or greater. the mcbsp data receive register (drr) and data transmit register (dxr) can be accessed through two separate busses: a configuration bus and a data bus. both paths can be used by the cpu and the edma. the data bus should be used to service the mcbsp as this path provides better performance. however, since the data path shares a bridge with the pci peripheral (see figure 4-1 ), the configuration path should be used in cases where this peripheral is being used to avoid any performance degradation. note that the pci peripheral consists of an independent master and slave. performance degradation is only a concern when this peripheral is used to initiate transactions on the external bus. 7.13.1.1 mcbsp peripheral register description(s) table 7-57. mcbsp 0 registers hex address range acronym register name comments the cpu and edma3 controller can only read 028c 0000 drr0 mcbsp0 data receive register via configuration bus this register; they cannot write to it. 3000 0000 drr0 mcbsp0 data receive register via edma3 bus 028c 0004 dxr0 mcbsp0 data transmit register via configuration bus 3000 0010 dxr0 mcbsp0 data transmit register via edma bus 028c 0008 spcr0 mcbsp0 serial port control register 028c 000c rcr0 mcbsp0 receive control register 028c 0010 xcr0 mcbsp0 transmit control register 028c 0014 srgr0 mcbsp0 sample rate generator register 028c 0018 mcr0 mcbsp0 multichannel control register mcbsp0 enhanced receive channel enable 028c 001c rcere00 register 0 partition a/b mcbsp0 enhanced transmit channel enable 028c 0020 xcere00 register 0 partition a/b 028c 0024 pcr0 mcbsp0 pin control register mcbsp0 enhanced receive channel enable 028c 0028 rcere10 register 1 partition c/d mcbsp0 enhanced transmit channel enable 028c 002c xcere10 register 1 partition c/d mcbsp0 enhanced receive channel enable 028c 0030 rcere20 register 2 partition e/f mcbsp0 enhanced transmit channel enable 028c 0034 xcere20 register 2 partition e/f mcbsp0 enhanced receive channel enable 028c 0038 rcere30 register 3 partition g/h mcbsp0 enhanced transmit channel enable 028c 003c xcere30 register 3 partition g/h 028c 0040 - 028f ffff - reserved c64x+ peripheral information and electrical specifications 178 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-58. mcbsp 1 registers hex address range acronym register name comments the cpu and edma controller can only read 0290 0000 drr1 mcbsp1 data receive register via configuration bus this register; they cannot write to it. 3400 0000 drr1 mcbsp1 data receive register via edma bus 0290 0004 dxr1 mcbsp1 data transmit register via configuration bus 3400 0010 dxr1 mcbsp1 data transmit register via edma bus 0290 0008 spcr1 mcbsp1 serial port control register 0290 000c rcr1 mcbsp1 receive control register 0290 0010 xcr1 mcbsp1 transmit control register 0290 0014 srgr1 mcbsp1 sample rate generator register 0290 0018 mcr1 mcbsp1 multichannel control register mcbsp1 enhanced receive channel enable 0290 001c rcere01 register 0 partition a/b mcbsp1 enhanced transmit channel enable 0290 0020 xcere01 register 0 partition a/b 0290 0024 pcr1 mcbsp1 pin control register mcbsp1 enhanced receive channel enable 0290 0028 rcere11 register 1 partition c/d mcbsp1 enhanced transmit channel enable 0290 002c xcere11 register 1 partition c/d mcbsp1 enhanced receive channel enable 0290 0030 rcere21 register 2 partition e/f mcbsp1 enhanced transmit channel enable 0290 0034 xcere21 register 2 partition e/f mcbsp1 enhanced receive channel enable 0290 0038 rcere31 register 3 partition g/h mcbsp1 enhanced transmit channel enable 0290 003c xcere31 register 3 partition g/h 0290 0040 - 0293 ffff - reserved submit documentation feedback c64x+ peripheral information and electrical specifications 179 product preview www.ti.com
7.13.2 mcbsp electrical data/timing TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 7.13.2.1 multichannel buffered serial port (mcbsp) timing table 7-59. timing requirements for mcbsp (1) (see figure 7-52 ) -720 -850 no. unit -1000 min max 2 t c(ckrx) cycle time, clkr/x clkr/x ext 6p or 10 (2) (3) ns 3 t w(ckrx) pulse duration, clkr/x high or clkr/x low clkr/x ext 0.5t c(ckrx) ? 1 (4) ns clkr int 9 5 t su(frh-ckrl) setup time, external fsr high before clkr low ns clkr ext 1.3 clkr int 6 6 t h(ckrl-frh) hold time, external fsr high after clkr low ns clkr ext 3 clkr int 8 7 t su(drv-ckrl) setup time, dr valid before clkr low ns clkr ext 0.9 clkr int 3 8 t h(ckrl-drv) hold time, dr valid after clkr low ns clkr ext 3.1 clkx int 9 10 t su(fxh-ckxl) setup time, external fsx high before clkx low ns clkx ext 1.3 clkx int 6 11 t h(ckxl-fxh) hold time, external fsx high after clkx low ns clkx ext 3 (1) clkrp = clkxp = fsrp = fsxp = 0. if polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) p = 1/cpu clock frequency in ns. for example, when running parts at 1000 mhz, use p = 1 ns. (3) use whichever value is greater. minimum clkr/x cycle times must be met, even when clkr/x is generated by an internal clock source. the minimum clkr/x cycle times are based on internal logic speed; the maximum usable speed may be lower due to edma limitations and ac timing requirements. (4) this parameter applies to the maximum mcbsp frequency. operate serial clocks (clkr/x) in the reasonable range of 40/60 duty cycle. table 7-60. switching characteristics over recommended operating conditions for mcbsp (1) (2) (see figure 7-52 ) -720 -850 no. parameter unit -1000 min max delay time, clks high to clkr/x high for internal clkr/x 1 t d(cksh-ckrxh) 1.4 10 ns generated from clks input (3) 2 t c(ckrx) cycle time, clkr/x clkr/x int 6p or 10 (4) (5) (6) ns (1) clkrp = clkxp = fsrp = fsxp = 0. if polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) minimum delay times also represent minimum output hold times. (3) the clks signal is shared by both mcbsp0 and mcbsp1 on this device. (4) minimum clkr/x cycle times must be met, even when clkr/x is generated by an internal clock source. minimum clkr/x cycle times are based on internal logic speed; the maximum usable speed may be lower due to edma limitations and ac timing requirements. (5) p = 1/cpu clock frequency in ns. for example, when running parts at 1000 mhz, use p = 1 ns. (6) use whichever value is greater. c64x+ peripheral information and electrical specifications 180 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-60. switching characteristics over recommended operating conditions for mcbsp (see figure 7-52 ) (continued) -720 -850 no. parameter unit -1000 min max 3 t w(ckrx) pulse duration, clkr/x high or clkr/x low clkr/x int c ? 1 (7) c + 1 (7) ns 4 t d(ckrh-frv) delay time, clkr high to internal fsr valid clkr int ?2.1 3.3 ns clkx int ?1.7 3 9 t d(ckxh-fxv) delay time, clkx high to internal fsx valid ns clkx ext 1.7 9 clkx int ?3.9 4 disable time, dx high impedance following 12 t dis(ckxh-dxhz) ns last data bit from clkx high clkx ext 2.1 9 clkx int ?3.9 + d1 (8) 4 + d2 (8) 13 t d(ckxh-dxv) delay time, clkx high to dx valid ns clkx ext 2.1 + d1 (8) 9 + d2 (8) delay time, fsx high to dx valid fsx int ?2.3 + d1 (9) 5.6 + d2 (9) 14 t d(fxh-dxv) ns only applies when in data fsx ext 1.9 + d1 (9) 9 + d2 (9) delay 0 (xdatdly = 00b) mode (7) c = h or l s = sample rate generator input clock = 6p if clksm = 1 (p = 1/cpu clock frequency) s = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even h = (clkgdv + 1)/2 * s if clkgdv is odd l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even l = (clkgdv + 1)/2 * s if clkgdv is odd clkgdv should be set appropriately to ensure the mcbsp bit rate does not exceed the maximum limit (see (4) above). (8) extra delay from clkx high to dx valid applies only to the first data bit of a device, if and only if dxena = 1 in spcr. if dxena = 0, then d1 = d2 = 0 if dxena = 1, then d1 = 6p, d2 = 12p (9) extra delay from fsx high to dx valid applies only to the first data bit of a device, if and only if dxena = 1 in spcr. if dxena = 0, then d1 = d2 = 0 if dxena = 1, then d1 = 6p, d2 = 12p submit documentation feedback c64x+ peripheral information and electrical specifications 181 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 a. parameter no. 13 applies to the first data bit only when xdatdly 1 0. b. the clks signal is shared by both mcbsp0 and mcbsp1 on this device. figure 7-52. mcbsp timing (b) table 7-61. timing requirements for fsr when gsync = 1 (see figure 7-53 ) -720 -850 no. unit -1000 min max 1 t su(frh-cksh) setup time, fsr high before clks high 4 ns 2 t h(cksh-frh) hold time, fsr high after clks high 4 ns figure 7-53. fsr timing when gsync = 1 182 c64x+ peripheral information and electrical specifications submit documentation feedback www.ti.com product preview bit(n-1) (n-2) (n-3) bit 0 bit(n-1) (n-2) (n-3) 14 12 11 10 9 3 3 2 8 7 6 5 4 4 3 1 3 2 clks clkr fsr (int) fsr (ext) dr clkx fsx (int) fsx (ext) fsx (xda tdly=00b) dx 13 (a) 13 (a) 2 1 clks fsr external clkr/x (no need to resync) clkr/x (needs resync)
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-62. timing requirements for mcbsp as spi master or slave: clkstp = 10b, clkxp = 0 (1) (2) (see figure 7-54 ) -720 -850 -1000 no. unit master slave min max min max 4 t su(drv-ckxl) setup time, dr valid before clkx low 12 2 ? 18p ns 5 t h(ckxl-drv) hold time, dr valid after clkx low 4 5 + 36p ns (1) p = 1/cpu clock frequency in ns. for example, when running parts at 1000 mhz, use p = 1 ns. (2) for all spi slave modes, clkg is programmed as 1/6 of the cpu clock by setting clksm = clkgdv = 1. table 7-63. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 10b, clkxp = 0 (1) (2) (see figure 7-54 ) -720 -850 -1000 no. parameter unit master (3) slave min max min max 1 t h(ckxl-fxl) hold time, fsx low after clkx low (4) t ? 2 t + 3 ns 2 t d(fxl-ckxh) delay time, fsx low to clkx high (5) l ? 2 l + 3 ns 3 t d(ckxh-dxv) delay time, clkx high to dx valid ?2 4 18p + 2.8 30p + 17 ns disable time, dx high impedance following 6 t dis(ckxl-dxhz) l ? 2 l + 3 ns last data bit from clkx low disable time, dx high impedance following 7 t dis(fxh-dxhz) 6p + 3 18p + 17 ns last data bit from fsx high 8 t d(fxl-dxv) delay time, fsx low to dx valid 12p + 2 24p + 17 ns (1) p = 1/cpu clock frequency in ns. for example, when running parts at 1000 mhz, use p = 1 ns. (2) for all spi slave modes, clkg is programmed as 1/6 of the cpu clock by setting clksm = clkgdv = 1. (3) s = sample rate generator input clock = 6p if clksm = 1 (p = 1/cpu clock frequency) s = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even h = (clkgdv + 1)/2 * s if clkgdv is odd l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even l = (clkgdv + 1)/2 * s if clkgdv is odd (4) fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp (5) fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of the master clock (clkx). figure 7-54. mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 0 submit documentation feedback c64x+ peripheral information and electrical specifications 183 product preview www.ti.com bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 5 4 3 8 76 2 1 clkx fsx dx dr
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-64. timing requirements for mcbsp as spi master or slave: clkstp = 11b, clkxp = 0 (1) (2) (see figure 7-55 ) -720 -850 -1000 no. unit master slave min max min max 4 t su(drv-ckxh) setup time, dr valid before clkx high 12 2 ? 18p ns 5 t h(ckxh-drv) hold time, dr valid after clkx high 4 5 + 36p ns (1) p = 1/cpu clock frequency in ns. for example, when running parts at 1000 mhz, use p = 1 ns. (2) for all spi slave modes, clkg is programmed as 1/6 of the cpu clock by setting clksm = clkgdv = 1. table 7-65. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 11b, clkxp = 0 (1) (2) (see figure 7-55 ) -720 -850 -1000 no. parameter unit master (3) slave min max min max 1 t h(ckxl-fxl) hold time, fsx low after clkx low (4) l ? 2 l + 3 ns 2 t d(fxl-ckxh) delay time, fsx low to clkx high (5) t ? 2 t + 3 ns 3 t d(ckxl-dxv) delay time, clkx low to dx valid ?2 4 18p + 2.8 30p + 17 ns disable time, dx high impedance following 6 t dis(ckxl-dxhz) ?2 4 18p + 3 30p + 17 ns last data bit from clkx low 7 t d(fxl-dxv) delay time, fsx low to dx valid h ? 2 h + 4 12p + 2 24p + 17 ns (1) p = 1/cpu clock frequency in ns. for example, when running parts at 1000 mhz, use p = 1 ns. (2) for all spi slave modes, clkg is programmed as 1/6 of the cpu clock by setting clksm = clkgdv = 1. (3) s = sample rate generator input clock = 6p if clksm = 1 (p = 1/cpu clock frequency) s = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even h = (clkgdv + 1)/2 * s if clkgdv is odd l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even l = (clkgdv + 1)/2 * s if clkgdv is odd (4) fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp (5) fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of the master clock (clkx). figure 7-55. mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 0 184 c64x+ peripheral information and electrical specifications submit documentation feedback www.ti.com product preview bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 4 3 7 6 2 1 clkx fsx dx dr 5
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-66. timing requirements for mcbsp as spi master or slave: clkstp = 10b, clkxp = 1 (1) (2) (see figure 7-56 ) -720 -850 -1000 no. unit master slave min max min max 4 t su(drv-ckxh) setup time, dr valid before clkx high 12 2 ? 18p ns 5 t h(ckxh-drv) hold time, dr valid after clkx high 4 5 + 36p ns (1) p = 1/cpu clock frequency in ns. for example, when running parts at 1000 mhz, use p = 1 ns. (2) for all spi slave modes, clkg is programmed as 1/6 of the cpu clock by setting clksm = clkgdv = 1. table 7-67. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 10b, clkxp = 1 (1) (2) (see figure 7-56 ) -720 -850 -1000 no. parameter unit master (3) slave min max min max 1 t h(ckxh-fxl) hold time, fsx low after clkx high (4) t ? 2 t + 3 ns 2 t d(fxl-ckxl) delay time, fsx low to clkx low (5) h ? 2 h + 3 ns 3 t d(ckxl-dxv) delay time, clkx low to dx valid ?2 4 18p + 2.8 30p + 17 ns disable time, dx high impedance following 6 t dis(ckxh-dxhz) h ? 2 h + 3 ns last data bit from clkx high disable time, dx high impedance following 7 t dis(fxh-dxhz) 6p + 3 18p + 17 ns last data bit from fsx high 8 t d(fxl-dxv) delay time, fsx low to dx valid 12p + 2 24p + 17 ns (1) p = 1/cpu clock frequency in ns. for example, when running parts at 1000 mhz, use p = 1 ns. (2) for all spi slave modes, clkg is programmed as 1/6 of the cpu clock by setting clksm = clkgdv = 1. (3) s = sample rate generator input clock = 6p if clksm = 1 (p = 1/cpu clock frequency) s = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even h = (clkgdv + 1)/2 * s if clkgdv is odd l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even l = (clkgdv + 1)/2 * s if clkgdv is odd (4) fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp (5) fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of the master clock (clkx). figure 7-56. mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 1 submit documentation feedback c64x+ peripheral information and electrical specifications 185 product preview www.ti.com bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 5 4 3 8 7 6 2 1 clkx fsx dx dr
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-68. timing requirements for mcbsp as spi master or slave: clkstp = 11b, clkxp = 1 (1) (2) (see figure 7-57 ) -720 -850 -1000 no. unit master slave min max min max 4 t su(drv-ckxh) setup time, dr valid before clkx high 12 2 ? 18p ns 5 t h(ckxh-drv) hold time, dr valid after clkx high 4 5 + 36p ns (1) p = 1/cpu clock frequency in ns. for example, when running parts at 1000 mhz, use p = 1 ns. (2) for all spi slave modes, clkg is programmed as 1/6 of the cpu clock by setting clksm = clkgdv = 1. table 7-69. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 11b, clkxp = 1 (1) (2) (see figure 7-57 ) -720 -850 -1000 no. parameter unit master (3) slave min max min max 1 t h(ckxh-fxl) hold time, fsx low after clkx high (4) h ? 2 h + 3 ns 2 t d(fxl-ckxl) delay time, fsx low to clkx low (5) t ? 2 t + 1 ns 3 t d(ckxh-dxv) delay time, clkx high to dx valid ?2 4 18p + 2.8 30p + 17 ns disable time, dx high impedance following 6 t dis(ckxh-dxhz) ?2 4 18p + 3 30p + 17 ns last data bit from clkx high 7 t d(fxl-dxv) delay time, fsx low to dx valid l ? 2 l + 4 12p + 2 24p + 17 ns (1) p = 1/cpu clock frequency in ns. for example, when running parts at 1000 mhz, use p = 1 ns. (2) for all spi slave modes, clkg is programmed as 1/6 of the cpu clock by setting clksm = clkgdv = 1. (3) s = sample rate generator input clock = 6p if clksm = 1 (p = 1/cpu clock frequency) s = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even h = (clkgdv + 1)/2 * s if clkgdv is odd l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even l = (clkgdv + 1)/2 * s if clkgdv is odd (4) fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp (5) fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of the master clock (clkx). figure 7-57. mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 1 186 c64x+ peripheral information and electrical specifications submit documentation feedback www.ti.com product preview bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 5 4 3 7 6 2 1 clkx fsx dx dr
7.14 ethernet mac (emac) TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the ethernet media access controller (emac) module provides an efficient interface between the c6454 dsp core processor and the networked community. the emac supports 10base-t (10 mbits/second [mbps]), and 100basetx (100 mbps), in either half- or full-duplex mode, and 1000baset (1000 mbps) in full-duplex mode, with hardware flow control and quality-of-service (qos) support. the emac module conforms to the ieee 802.3-2002 standard, describing the ?carrier sense multiple access with collision detection (csma/cd) access method and physical layer? specifications. the ieee 802.3 standard has also been adopted by iso/iec and re-designated as iso/iec 8802-3:2000(e). deviation from this standard, the emac module does not use the transmit coding error signal mtxer. instead of driving the error pin when an underflow condition occurs on a transmitted frame, the emac will intentionally generate an incorrect checksum by inverting the frame crc, so that the transmitted frame will be detected as an error by the network. the emac control module is the main interface between the device core processor, the mdio module, and the emac module. the relationship between these three components is shown in figure 7-58 . the emac control module contains the necessary components to allow the emac to make efficient use of device memory, plus it controls device interrupts. the emac control module incorporates 8k-bytes of internal ram to hold emac buffer descriptors. the relationship between these three components is shown in figure 7-58 . figure 7-58. emac, mdio, and emac control modules for more detailed information on the emac/mdio, see the tms320c645x dsp emac/mdio module reference guide (literature number spru975 ). submit documentation feedback c64x+ peripheral information and electrical specifications 187 product preview www.ti.com configuration bus dma memory t ransfer controller peripheral bus emac control module emac module mdio module mdio bus emac/mdio interrupt interrupt controller ethernet bus
7.14.1 emac device-specific information TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 interface modes the emac module on the TMS320C6454 supports four interface modes: media independent interface (mii), reduced media independent interface (rmii), gigabit media independent interface (gmii), and reduced gigabit media independent interface (rgmii). the mii and gmii interface modes are defined in the ieee 802.3-2002 standard. the rgmii mode of the emac conforms to the reduced gigabit media independent interface (rgmii) specification (version 2.0). the rgmii mode implements the same functionality as the gmii mode, but with a reduced number of pins. data and control information is transmitted and received using both edges of the transmit and receive clocks (txc and rxc). note: the emac internally delays the transmit clock (txc) with respect to the transmit data and control pins. therefore, the emac conforms to the rgmii-id operation of the rgmii specification. however, the emac does not delay the receive clock (rxc); this signal must be delayed with respect to the receive data and control pins outside of the dsp. the rmii mode of the emac conforms to the rmii specification (revision 1.2), as written by the rmii consortium. as the name implies, the reduced media independent interface (rmii) mode is a reduced pin count version of the mii mode. interface mode select the emac uses the same pins for the mii, gmii, and rmii modes. standalone pins are included for the rgmii mode due to specific voltage requirements. only one mode can be used at a time. the mode used is selected at device reset based on the macsel[1:0] configuration pins (for more detailed information, see section 3 , device configuration). table 7-70 shows which multiplexed pins are used in the mii, gmii, and rmii modes on the emac. for a detailed description of these pin functions, see table 2-3 , terminal functions. 188 c64x+ peripheral information and electrical specifications submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-70. emac/mdio multiplexed pins (mii, rmii, and gmii modes) ball number device pin name mii rmii gmii (mac_sel = (mac_sel = (mac_sel = 00b) 01b) 10b) j2 mrxd0/rmrxd0 mrxd0 rmrxd0 mrxd0 h3 mrxd1/rmrxd1 mrxd1 rmrxd1 mrxd1 j1 mrxd2 mrxd2 mrxd2 j3 mrxd3 mrxd3 mrxd3 l1 mrxd4 mrxd4 l2 mrxd5 mrxd5 h2 mrxd6 mrxd6 m2 mrxd7 mrxd7 m1 mtxd0/rmtxd0 mtxd0 rmtxd0 mtxd0 l4 mtxd1/rmtxd1 mtxd1 rmtxd1 mtxd1 m4 mtxd2 mtxd2 mtxd2 k4 mtxd3 mtxd3 mtxd3 l3 mtxd4 mtxd4 l5 mtxd5 mtxd5 m3 mtxd6 mtxd6 n5 mtxd7 mtxd7 h4 mrxer/rmrxer mrxer rmrxer mrxer h5 mrxdv mrxdv mrxdv j5 mtxen/rmtxen mtxen rmtxen mtxen j4 mcrs/rmcrsdv mcrs rmcrsdv mcrs k3 mcol mcol mcol k5 gmtclk gmtclk h1 mrclk mrclk mrclk n4 mtclk/refclk mtclk rmrefclk mtclk n3 gmdio mdio mdio mdio m5 gmdclk mdclk mdclk mdclk using the rmii mode of the emac the ethernet media access controller (emac) contains logic that allows it to communicate using the reduced media independent interface (rmii) protocol. this logic must be taken out of reset before being used. to use the rmii mode of the emac follow these steps: 1. enable the emac/mdio through the device state control registers. ? unlock the percfg0 register by writing 0x0f0a 0b00 to the perlock register. ? set bit 4 in the percfg0 register within 16 sysclk3 clock cycles to enable the emac/mdio. ? poll the perstat0 register to verify state change. 2. initialize the emac/mdio as needed. 3. release the rmii logic from reset by clearing the rmii_rst bit of the emac configuration register (see section 3.4.5 ). as described in the previous section, the rmii mode of the emac must be selected by setting macsel[1:0] = 01b at device reset. submit documentation feedback c64x+ peripheral information and electrical specifications 189 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 interface mode clocking the on-chip pll2 and pll2 controller generate all the clocks to the emac module. when enabled, the input clock to the pll2 controller (clkin2) must have a 25 mhz frequency. for more information, see section 7.8 , pll2 and pll2 controller. the emac uses sysclk1 of the pll2 controller to generate the necessary clocks for the gmii and rgmii modes. when these modes are used, the frequency of clkin2 must be 25 mhz. also, divider d1 should be programmed to ? 2 mode [default] when using the gmii mode and to ? 5 mode when using the rgmii mode. divider d1 is software programmable and, if necessary, must be programmed after device reset to ? 5 when the rgmii mode of the emac is used. 190 c64x+ peripheral information and electrical specifications submit documentation feedback www.ti.com product preview
7.14.2 emac peripheral register description(s) TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-71. ethernet mac (emac) control registers hex address range acronym register name 02c8 0000 txidver transmit identification and version register 02c8 0004 txcontrol transmit control register 02c8 0008 txteardown transmit teardown register 02c8 000f - reserved 02c8 0010 rxidver receive identification and version register 02c8 0014 rxcontrol receive control register 02c8 0018 rxteardown receive teardown register 02c8 001c - reserved 02c8 0020 - 02c8 007c - reserved 02c8 0080 txintstatraw transmit interrupt status (unmasked) register 02c8 0084 txintstatmasked transmit interrupt status (masked) register 02c8 0088 txintmaskset transmit interrupt mask set register 02c8 008c txintmaskclear transmit interrupt mask clear register 02c8 0090 macinvector mac input vector register 02c8 0194 - 02c8 019c - reserved 02c8 01a0 rxintstatraw receive interrupt status (unmasked) register 01c8 01a4 rxintstatmasked receive interrupt status (masked) register 01c8 01a8 rxintmaskset receive interrupt mask set register 01c8 01ac rxintmaskclear receive interrupt mask clear register 01c8 01b0 macintstatraw mac interrupt status (unmasked) register 01c8 01b4 macintstatmasked mac interrupt status (masked) register 01c8 01b8 macintmaskset mac interrupt mask set register 01c8 01bc macintmaskclear mac interrupt mask clear register 02c8 00c0 - 02c8 00fc - reserved 02c8 0100 rxmbpenable receive multicast/broadcast/promiscuous channel enable register 02c8 0104 rxunicastset receive unicast enable set register 02c8 0108 rxunicastclear receive unicast clear register 02c8 010c rxmaxlen receive maximum length register 02c8 0110 rxbufferoffset receive buffer offset register 02c8 0114 rxfilterlowthresh receive filter low priority frame threshold register 02c8 0118 - 02c8 011c - reserved 02c8 0120 rx0flowthresh receive channel 0 flow control threshold register 02c8 0124 rx1flowthresh receive channel 1 flow control threshold register 02c8 0128 rx2flowthresh receive channel 2 flow control threshold register 02c8 012c rx3flowthresh receive channel 3 flow control threshold register 02c8 0130 rx4flowthresh receive channel 4 flow control threshold register 02c8 0134 rx5flowthresh receive channel 5 flow control threshold register 02c8 0138 rx6flowthresh receive channel 6 flow control threshold register 02c8 013c rx7flowthresh receive channel 7 flow control threshold register 02c8 0140 rx0freebuffer receive channel 0 free buffer count register 02c8 0144 rx1freebuffer receive channel 1 free buffer count register 02c8 0148 rx2freebuffer receive channel 2 free buffer count register 02c8 014c rx3freebuffer receive channel 3 free buffer count register 02c8 0150 rx4freebuffer receive channel 4 free buffer count register submit documentation feedback c64x+ peripheral information and electrical specifications 191 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-71. ethernet mac (emac) control registers (continued) hex address range acronym register name 02c8 0154 rx5freebuffer receive channel 5 free buffer count register 02c8 0158 rx6freebuffer receive channel 6 free buffer count register 02c8 015c rx7freebuffer receive channel 7 free buffer count register 02c8 0160 maccontrol mac control register 02c8 0164 macstatus mac status register 02c8 0168 emcontrol emulation control register 02c8 016c fifocontrol fifo control register (transmit and receive) 02c8 0170 macconfig mac configuration register 02c8 0174 softreset soft reset register 02c8 0178 - 02c8 01cc - reserved 02c8 01d0 macsrcaddrlo mac source address low bytes register (lower 32-bits) 02c8 01d4 macsrcaddrhi mac source address high bytes register (upper 32-bits) 02c8 01d8 machash1 mac hash address register 1 02c8 01dc machash2 mac hash address register 2 02c8 01e0 bofftest back off test register 02c8 01e4 tpacetest transmit pacing algorithm test register 02c8 01e8 rxpause receive pause timer register 02c8 01ec txpause transmit pause timer register 02c8 01f0 - 02c8 01fc - reserved 02c8 0200 - 02c8 02fc (see table 7-72 ) emac statistics registers 02c8 0300 - 02c8 03fc - reserved 02c8 0400 - 02c8 04fc - reserved mac address low bytes register (used in receive address 02c8 0500 macaddrlo matching) mac address high bytes register (used in receive address 02c8 0504 macaddrhi matching) 02c8 0508 macindex mac index register 02c8 050c - 02c8 05fc - reserved 02c8 0600 tx0hdp transmit channel 0 dma head descriptor pointer register 02c8 0604 tx1hdp transmit channel 1 dma head descriptor pointer register 02c8 0608 tx2hdp transmit channel 2 dma head descriptor pointer register 02c8 060c tx3hdp transmit channel 3 dma head descriptor pointer register 02c8 0610 tx4hdp transmit channel 4 dma head descriptor pointer register 02c8 0614 tx5hdp transmit channel 5 dma head descriptor pointer register 02c8 0618 tx6hdp transmit channel 6 dma head descriptor pointer register 02c8 061c tx7hdp transmit channel 7 dma head descriptor pointer register 02c8 0620 rx0hdp receive channel 0 dma head descriptor pointer register 02c8 0624 rx1hdp receive channel 1 dma head descriptor pointer register 02c8 0628 rx2hdp receive channel 2 dma head descriptor pointer register 02c8 062c rx3hdp receive channel 3 dma head descriptor pointer register 02c8 0630 rx4hdp receive channel 4 dma head descriptor pointer register 02c8 0634 rx5hdp receive channel 5 dma head descriptor pointer register 02c8 0638 rx6hdp receive channel 6 dma head descriptor pointer register 02c8 063c rx7hdp receive channel 7 dma head descriptor pointer register transmit channel 0 completion pointer (interrupt acknowledge) 02c8 0640 tx0cp register transmit channel 1 completion pointer (interrupt acknowledge) 02c8 0644 tx1cp register c64x+ peripheral information and electrical specifications 192 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-71. ethernet mac (emac) control registers (continued) hex address range acronym register name transmit channel 2 completion pointer (interrupt acknowledge) 02c8 0648 tx2cp register transmit channel 3 completion pointer (interrupt acknowledge) 02c8 064c tx3cp register transmit channel 4 completion pointer (interrupt acknowledge) 02c8 0650 tx4cp register transmit channel 5 completion pointer (interrupt acknowledge) 02c8 0654 tx5cp register transmit channel 6 completion pointer (interrupt acknowledge) 02c8 0658 tx6cp register transmit channel 7 completion pointer (interrupt acknowledge) 02c8 065c tx7cp register receive channel 0 completion pointer (interrupt acknowledge) 02c8 0660 rx0cp register receive channel 1 completion pointer (interrupt acknowledge) 02c8 0664 rx1cp register receive channel 2 completion pointer (interrupt acknowledge) 02c8 0668 rx2cp register receive channel 3 completion pointer (interrupt acknowledge) 02c8 066c rx3cp register receive channel 4 completion pointer (interrupt acknowledge) 02c8 0670 rx4cp register receive channel 5 completion pointer (interrupt acknowledge) 02c8 0674 rx5cp register receive channel 6 completion pointer (interrupt acknowledge) 02c8 0678 rx6cp register receive channel 7 completion pointer (interrupt acknowledge) 02c8 067c rx7cp register 02c8 0680 - 02c8 06fc - reserved reserved was state ram test access registers 02c8 0700 - 02c8 077c - processor read and write access to head descriptor pointers and interrupt acknowledge registers 02c8 0780 - 02c8 0fff - reserved table 7-72. emac statistics registers hex address range acronym register name 02c8 0200 rxgoodframes good receive frames register broadcast receive frames register 02c8 0204 rxbcastframes (total number of good broadcast frames received) multicast receive frames register 02c8 0208 rxmcastframes (total number of good multicast frames received) 02c8 020c rxpauseframes pause receive frames register receive crc errors register (total number of frames received with 02c8 0210 rxcrcerrors crc errors) receive alignment/code errors register 02c8 0214 rxaligncodeerrors (total number of frames received with alignment/code errors) receive oversized frames register 02c8 0218 rxoversized (total number of oversized frames received) receive jabber frames register 02c8 021c rxjabber (total number of jabber frames received) receive undersized frames register 02c8 0220 rxundersized (total number of undersized frames received) 02c8 0224 rxfragments receive frame fragments register submit documentation feedback c64x+ peripheral information and electrical specifications 193 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-72. emac statistics registers (continued) hex address range acronym register name 02c8 0228 rxfiltered filtered receive frames register 02c8 022c rxqosfiltered received qos filtered frames register receive octet frames register 02c8 0230 rxoctets (total number of received bytes in good frames) good transmit frames register 02c8 0234 txgoodframes (total number of good frames transmitted) 02c8 0238 txbcastframes broadcast transmit frames register 02c8 023c txmcastframes multicast transmit frames register 02c8 0240 txpauseframes pause transmit frames register 02c8 0244 txdeferred deferred transmit frames register 02c8 0248 txcollision transmit collision frames register 02c8 024c txsinglecoll transmit single collision frames register 02c8 0250 txmulticoll transmit multiple collision frames register 02c8 0254 txexcessivecoll transmit excessive collision frames register 02c8 0258 txlatecoll transmit late collision frames register 02c8 025c txunderrun transmit underrun error register 02c8 0260 txcarriersense transmit carrier sense errors register 02c8 0264 txoctets transmit octet frames register 02c8 0268 frame64 transmit and receive 64 octet frames register 02c8 026c frame65t127 transmit and receive 65 to 127 octet frames register 02c8 0270 frame128t255 transmit and receive 128 to 255 octet frames register 02c8 0274 frame256t511 transmit and receive 256 to 511 octet frames register 02c8 0278 frame512t1023 transmit and receive 512 to 1023 octet frames register 02c8 027c frame1024tup transmit and receive 1024 to 1518 octet frames register 02c8 0280 netoctets network octet frames register 02c8 0284 rxsofoverruns receive fifo or dma start of frame overruns register 02c8 0288 rxmofoverruns receive fifo or dma middle of frame overruns register receive dma start of frame and middle of frame overruns 02c8 028c rxdmaoverruns register 02c8 0290 - 02c8 02fc - reserved table 7-73. emac control module registers hex address range acronym register name 02c8 1000 - reserved 02c8 1004 ewctl emac control module interrupt control register 02c8 1008 ewinttcnt emac control module interrupt timer count register 02c8 100c - 02c8 17ff - reserved table 7-74. emac descriptor memory hex address range acronym description 02c8 2000 - 02c8 3fff - emac descriptor memory c64x+ peripheral information and electrical specifications 194 submit documentation feedback www.ti.com product preview
7.14.3 emac electrical data/timing TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 7.14.3.1 emac mii and gmii electrical data/timing table 7-75. timing requirements for mrclk - mii and gmii operation (see figure 7-59 ) -720 -850 -1000 no. unit 1000 mbps 100 mbps 10 mbps (gmii only) min max min max min max 1 t c(mrclk) cycle time, mrclk 8 40 400 ns 2 t w(mrclkh) pulse duration, mrclk high 2.8 14 140 ns 3 t w(mrclkl) pulse duration, mrclk low 2.8 14 140 ns 4 t t(mrclk) transition time, mrclk 1 3 3 ns figure 7-59. mrclk timing (emac ? receive) [mii and gmii operation] table 7-76. timing requirements for mtclk - mii and gmii operation (see figure 7-60 ) -720 -850 -1000 no. unit 100 mbps 10 mbps min max min max 1 t c(mtclk) cycle time, mtclk 40 400 ns 2 t w(mtclkh) pulse duration, mtclk high 14 140 ns 3 t w(mtclkl) pulse duration, mtclk low 14 140 ns 4 t t(mtclk) transition time, mtclk 3 3 ns figure 7-60. mtclk timing (emac ? transmit) [mii and gmii operation] submit documentation feedback c64x+ peripheral information and electrical specifications 195 product preview www.ti.com mrclk (input) 2 3 1 4 4 mtclk (input) 2 3 1 4 4
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-77. switching characteristics over recommended operating conditions for gmtclk - gmii operation (see figure 7-61 ) -720 -850 -1000 no. unit 1000 mbps min max 1 t c(gmtclk) cycle time, gmtclk 8 ns 2 t w(gmtclkh) pulse duration, gmtclk high 2.8 ns 3 t w(gmtclkl) pulse duration, gmtclk low 2.8 ns 4 t t(gmtclk) transition time, gmtclk 1 ns figure 7-61. gmtclk timing (emac ? transmit) [gmii operation] table 7-78. timing requirements for emac mii and gmii receive 10/100/1000 mbit/s (1) (see figure 7-62 ) -720 -850 -1000 no. unit 1000 mbps 100/10 mbps min max min max setup time, receive selected signals valid before 1 t su(mrxd-mrclkh) 2 8 ns mrclk high hold time, receive selected signals valid after 2 t h(mrclkh-mrxd) 0 8 ns mrclk high (1) for mii, receive selected signals include: mrxd[3:0], mrxdv, and mrxer. for gmii, receive selected signals include: mrxd[7:0], mrxdv, and mrxer. figure 7-62. emac receive interface timing [mii and gmii operation] c64x+ peripheral information and electrical specifications 196 submit documentation feedback www.ti.com product preview gmtclk(output) 2 3 1 4 4 mrclk (input) 1 2 mrxd7?mrxd4(gmii only), mrxd3?mrxd0, mrxdv , mrxer (inputs)
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-79. switching characteristics over recommended operating conditions for emac mii and gmii transmit 10/100 mbit/s (1) (see figure 7-63 ) -720 -850 -1000 no. parameter unit 100/10 mbps min max 1 t d(mtclkh-mtxd) delay time, mtclk high to transmit selected signals valid 5 25 ns (1) for mii, transmit selected signals include: mtxd[3:0] and mtxen. for gmii, transmit selected signals include: gmtxd[7:0] and mtxen. figure 7-63. emac transmit interface timing [mii and gmii operation] table 7-80. switching characteristics over recommended operating conditions for emac gmii transmit 1000 mbit/s (1) (see figure 7-64 ) -720 -850 -1000 no. parameter unit 1000 mbps min max 1 t d(gmtclkh-mtxd) delay time, gmtclk high to transmit selected signals valid 0.5 5 ns (1) for gmii, transmit selected signals include: gmtxd[7:0] and mtxen. figure 7-64. emac transmit interface timing [gmii operation] submit documentation feedback c64x+ peripheral information and electrical specifications 197 product preview www.ti.com 1 mtclk (input) mtxd7?mtxd4(gmii only), mtxd3?mtxd0, mtxen (outputs) 1 gmtclk (output) mtxd7?mtxd0, mtxen (outputs)
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 7.14.3.2 emac rmii electrical data/timing the rmrefclk pin is used to source a clock to the emac when it is configured for rmii operation. the rmrefclk frequency should be 50 mhz 50 ppm with a duty cycle between 35% and 65%, inclusive. table 7-81. timing requirements for rmrefclk - rmii operation (see figure 7-65 ) -720 -850 no. parameter unit -1000 min max 1 t w(rmrefclkh) pulse duration, rmrefclk high 7 13 ns 2 t w(rmrefclkl) pulse duration, rmrefclk low 7 13 ns 3 t t(rmrefclk) transition time, rmrefclk 2 ns figure 7-65. rmrefclk timing table 7-82. switching characteristics over recommended operating conditions for emac rmii transmit 10/100 mbit/s (1) (see figure 7-66 ) -720 -850 -1000 no. parameter unit 1000 mbps min max 1 t d(rmrefclkh-mtxd) delay time, rmrefclk high to transmit selected signals valid 3 10 ns (1) for rmii, transmit selected signals include: mtxd[1:0] and mtxen. figure 7-66. emac transmit interface timing [rmii operation] 198 c64x+ peripheral information and electrical specifications submit documentation feedback www.ti.com product preview rmrefclk (input) 1 2 3 3 1 rmrefclk (input) mtxd1-mtxd0, mtxen (outputs)
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-83. timing requirements for emac rmii input receive for 100 mbps (1) (see figure 7-67 ) -720 -850 no. unit -1000 min max setup time, receive selected signals valid before mrefclk (at dsp) 1 t su(mrxd-mrefclk) 4.0 ns high/low 2 t h(mrefclk-mrxd) hold time, receive selected signals valid after mrefclk (at dsp) high/low 2.0 ns (1) for rmii, receive selected signals include: mrxd[1:0], mrxer, and mcrsdv. figure 7-67. emac receive interface timing [rmii operation] submit documentation feedback c64x+ peripheral information and electrical specifications 199 product preview www.ti.com rmrefclk (input) 1 2 3 3 4 5 mrxd1-mrxd0, mcrsdv, mrxer (inputs)
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 7.14.3.3 emac rgmii electrical data/timing an extra clock signal, rgrefclk, running at 125 mhz is included as a convenience to the user. note that this reference clock is not a free-running clock. this should only be used by an external device if it does not expect a valid clock during device reset. table 7-84. switching characteristics over recommended operating conditions for emac rgrefclk - rgmii operation (see figure 7-68 ) -720 -850 no. parameter unit -1000 min max 1 t c(rgfclk) cycle time, rgrefclk 8 - 0.8 8 + 0.8 ns 2 t w(rgfclkh) pulse duration, rgrefclk high 3.2 4.8 ns 3 t w(rgfclkl) pulse duration, rgrefclk low 3.2 4.8 ns 4 t t(rgfclk) transition time, rgrefclk 0.75 ns figure 7-68. rgrefclk timing table 7-85. timing requirements for rxc - rgmii operation (see figure 7-69 ) -720 -850 no. unit -1000 min max 10 mbps 360 440 1 t c(rxc) cycle time, rxc 100 mbps 36 44 ns 1000 mbps 7.2 8.8 10 mbps 0.40*t c(rxc) 0.60*t c(rxc) 2 t w(rxch) pulse duration, rxc high 100 mbps 0.40*t c(rxc) 0.60*t c(rxc) ns 1000 mbps 0.45*t c(rxc) 0.55*t c(rxc) 10 mbps 0.40*t c(rxc) 0.60*t c(rxc) 3 t w(rxcl) pulse duration, rxc low 100 mbps 0.40*t c(rxc) 0.60*t c(rxc) ns 1000 mbps 0.45*t c(rxc) 0.55*t c(rxc) 10 mbps 0.75 4 t t(rxc) transition time, rxc 100 mbps 0.75 ns 1000 mbps 0.75 200 c64x+ peripheral information and electrical specifications submit documentation feedback www.ti.com product preview rgrefclk (output) 2 3 4 4 1
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-86. timing requirements for emac rgmii input receive for 10/100/1000 mbps (1) (see figure 7-69 ) -720 -850 no. unit -1000 min max 5 t su(rxd-rxch) setup time, receive selected signals valid before rxc (at dsp) high/low 1.0 ns 6 t h(rxch-rxd) hold time, receive selected signals valid after rxc (at dsp) high/low 1.0 ns (1) for rgmii, receive selected signals include: rxd[3:0] and rxctl. a. data and control information is received using both edges of the clocks. rxd[3:0] carries data bits 3-0 on the rising edge of rxc and data bits 7-4 on the falling edge of rxc. similarly, rxctl carries rxdv on rising edge of rxc and rxerr on falling edge b. rxc must be externally delayed relative to the data and control pins. figure 7-69. emac receive interface timing [rgmii operation] (a)(b) table 7-87. switching characteristics over recommended operating conditions for txc - rgmii operation for 10/100/1000 mbit/s (see figure 7-70 ) -720 -850 no. unit -1000 min max 10 mbps 360 440 1 t c(txc) cycle time, txc 100 mbps 36 44 ns 1000 mbps 7.2 8.8 10 mbps 0.40*t c(txc) 0.60*t c(txc) 2 t w(txch) pulse duration, txc high 100 mbps 0.40*t c(txc) 0.60*t c(txc) ns 1000 mbps 0.45*t c(txc) 0.55*t c(txc) 10 mbps 0.40*t c(txc) 0.60*t c(txc) 3 t w(txcl) pulse duration, txc low 100 mbps 0.40*t c(txc) 0.60*t c(txc) ns 1000 mbps 0.45*t c(txc) 0.55*t c(txc) 10 mbps 0.75 4 t t(txc) transition time, txc 100 mbps 0.75 ns 1000 mbps 0.75 submit documentation feedback c64x+ peripheral information and electrical specifications 201 product preview www.ti.com rxd[3:0] (a) rxctl (a) rxc (at dsp) (b) 5 rxerr rxdv 6 1st half-byte 2nd half-byte rxd[7:4] rxd[3:0] 2 3 1 4 4
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-88. switching characteristics over recommended operating conditions for emac rgmii transmit (1) (see figure 7-70 ) -720 -850 no. parameter unit -1000 min max 5 t su(txd-txch) setup time, transmit selected signals valid before txc (at dsp) high/low 1.2 ns 6 t h(txch-txd) hold time, transmit selected signals valid after txc (at dsp) high/low 1.2 (1) for rgmii, transmit selected signals include: txd[3:0] and txctl. a. data and control information is transmitted using both edges of the clocks. txd[3:0] carries data bits 3-0 on the rising edge of txc and data bits 7-4 on the falling edge of txc. similarly, tx_ctl carries txen on rising edge of txc and txerr of falling edge. b. txc is delayed internally before being driven to the txc pin. figure 7-70. emac transmit interface timing [rgmii operation] (a)(b) 202 c64x+ peripheral information and electrical specifications submit documentation feedback www.ti.com product preview txc (at dsp) (b) txd[3:0] (a) txctl (a) 5 6 1st half-byte txerr txen 2nd half-byte 1 2 internal txc txc at dsp pins 4 4 2 3 1
7.14.4 management data input/output (mdio) TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the management data input/output (mdio) module implements the 802.3 serial management interface to interrogate and controls up to 32 ethernet phy(s) connected to the device, using a shared two-wire bus. application software uses the mdio module to configure the auto-negotiation parameters of each phy attached to the emac, retrieve the negotiation results, and configure required parameters in the emac module for correct operation. the module is designed to allow almost transparent operation of the mdio interface, with very little maintenance from the core processor. the emac control module is the main interface between the device core processor, the mdio module, and the emac module. the relationship between these three components is shown in figure 7-58 . the mdio uses the same pins for the mii, gmii, and rmii modes. standalone pins are included for the rgmii mode due to specific voltage requirements. only one mode can be used at a time. the mode used is selected at device reset based on the macsel[1:0] configuration pins (for more detailed information, see section 3 , device configuration). table 7-70 above shows which multiplexed pin are used in the mii, gmii, and rmii modes on the mdio. for more detailed information on the emac/mdio, see the tms320c645x dsp emac/mdio module reference guide (literature number spru975 ). 7.14.4.1 mdio device-specific information clocking information the mdio clock is based on a divide-down of the sysclk3 (from the pll1 controller) and is specified to run up to 2.5 mhz, although typical operation is 1.0 mhz. since the peripheral clock frequency is variable, the application software or driver controls the divide-down amount. 7.14.4.2 mdio peripheral register description(s) table 7-89. mdio registers hex address range acronym register name 02c8 1800 version mdio version register 02c8 1804 control mdio control register 02c8 1808 alive mdio phy alive status register 02c8 180c link mdio phy link status register 02c8 1810 linkintraw mdio link status change interrupt (unmasked) register 02c8 1814 linkintmasked mdio link status change interrupt (masked) register 02c8 1818 - 02c8 181c - reserved 02c8 1820 userintraw mdio user command complete interrupt (unmasked) register 02c8 1824 userintmasked mdio user command complete interrupt (masked) register 02c8 1828 userintmaskset mdio user command complete interrupt mask set register 02c8 182c userintmaskclear mdio user command complete interrupt mask clear register 02c8 1830 - 02c8 187c - reserved 02c8 1880 useraccess0 mdio user access register 0 02c8 1884 userphysel0 mdio user phy select register 0 02c8 1888 useraccess1 mdio user access register 1 02c8 188c userphysel1 mdio user phy select register 1 02c8 1890 - 02c8 1fff - reserved submit documentation feedback c64x+ peripheral information and electrical specifications 203 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 7.14.4.3 mdio electrical data/timing table 7-90. timing requirements for mdio input (r)(g)mii (see figure 7-71 ) -720 -850 no. unit -1000 min max 1 t c(mdclk) cycle time, mdclk 400 ns 2a t w(mdclk) pulse duration, mdclk high 180 ns 2b t w(mdclk) pulse duration, mdclk low 180 ns 3 t t(mdclk) transition time, mdclk 5 ns 4 t su(mdio-mdclkh) setup time, mdio data input valid before mdclk high 10 ns 5 t h(mdclkh-mdio) hold time, mdio data input valid after mdclk high 10 ns figure 7-71. mdio input timing table 7-91. switching characteristics over recommended operating conditions for mdio output (see figure 7-72 ) -720 -850 no. parameter unit -1000 min max 7 t d(mdclkl-mdio) delay time, mdclk low to mdio data output valid 100 ns figure 7-72. mdio output timing 204 c64x+ peripheral information and electrical specifications submit documentation feedback www.ti.com product preview 1 3 4 mdclk mdio (input) 1 7 mdclk mdio (output)
7.15 timers 7.15.1 timers device-specific information 7.15.2 timers peripheral register description(s) TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the timers can be used to: time events, count events, generate pulses, interrupt the cpu, and send synchronization events to the edma3 channel controller. the c6454 device has two general-purpose timers, timer0 and timer1, each of which can be configured as a general-purpose timer or a watchdog timer. when configured as a general-purpose timer, each timer can be programmed as a 64-bit timer or as two separate 32-bit timers. each timer is made up of two 32-bit counters: a high counter and a low counter. the timer pins, tinplx and toutlx are connected to the low counter. the high counter does not have any external device pins. table 7-92. timer 0 registers hex address range acronym register name comments 0294 0000 - reserved timer 0 emulation management/clock speed 0294 0004 emumgt_clkspd0 register 0294 0008 - reserved 0294 000c - reserved 0294 0010 cntlo0 timer 0 counter register low 0294 0014 cnthi0 timer 0 counter register high 0294 0018 prdlo0 timer 0 period register low 0294 001c prdhi0 timer 0 period register high 0294 0020 tcr0 timer 0 control register 0294 0024 tgcr0 timer 0 global control register 0294 0028 wdtcr0 timer 0 watchdog timer control register 0294 002c - reserved 0294 0030 - reserved 0294 0034 - 0297 ffff - reserved table 7-93. timer 1 registers hex address range acronym register name comments 0298 0000 - reserved 0298 0004 emumgt_clkspd1 timer 1 emulation management/clock speed register 0298 0008 - reserved 0298 000c - reserved 0298 0010 cntlo1 timer 1 counter register low 0298 0014 cnthi1 timer 1 counter register high 0298 0018 prdlo1 timer 1 period register low 0298 001c prdhi1 timer 1 period register high 0298 0020 tcr1 timer 1 control register 0298 0024 tgcr1 timer 1 global control register 0298 0028 wdtcr1 timer 1 watchdog timer control register 0298 002c - reserved 0298 0030 - reserved 0298 0034 - 0299 ffff - reserved submit documentation feedback c64x+ peripheral information and electrical specifications 205 product preview www.ti.com
7.15.3 timers electrical data/timing TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-94. timing requirements for timer inputs (1) (see figure 7-73 ) -720 -850 no. unit -1000 min max 1 t w(tinph) pulse duration, tinplx high 12p ns 2 t w(tinpl) pulse duration, tinplx low 12p ns (1) p = 1/cpu clock frequency in ns. for example, when running parts at 1000 mhz, use p = 1 ns. table 7-95. switching characteristics over recommended operating conditions for timer outputs (1) (see figure 7-73 ) -720 -850 no. parameter unit -1000 min max 3 t w(touth) pulse duration, toutlx high 12p ? 3 ns 4 t w(toutl) pulse duration, toutlx low 12p ? 3 ns (1) p = 1/cpu clock frequency in ns. for example, when running parts at 1000 mhz, use p = 1 ns. figure 7-73. timer timing 206 c64x+ peripheral information and electrical specifications submit documentation feedback www.ti.com product preview tinplx toutlx 4 3 2 1
7.16 peripheral component interconnect (pci) 7.16.1 pci device-specific information TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 the c6454 dsp supports connections to a pci backplane via the integrated pci master/slave bus interface. the pci port interfaces to dsp internal resources via the data switched central resource. the data switched central resource is described in more detail in section 4 . for more detailed information on the pci port peripheral module, see the tms320c645x dsp peripheral component interconnect (pci) user's guide (literature number sprue60 ). the pci peripheral on the c6454 dsp conforms to the pci local bus specification (version 2.3). the pci peripheral can act both as a pci bus master and as a target. it supports pci bus operation of speeds up to 66 mhz and uses a 32-bit data/address bus. on the c6454 device, the pins of the pci peripheral are multiplexed with the pins of the hpi and gpio peripherals. pci functionality for these pins is controlled (enabled/disabled) by the pci_en pin (y29). the maximum speed of the pci, 33 mhz or 66 mhz, is controlled through the pci66 pin (u27). for more detailed information on the peripheral control, see section 3 , device configuration. the c6454 device provides an initialization mechanism through which the default values for some of the pci configuration registers can be read from an i2c eeprom. table 7-96 shows the registers which can be initialized through the pci auto-initialization. also shown is the default value of these registers when pci auto-initialization is not used. pci auto-initialization is controlled (enabled/disabled) through the pci_eeai pin (p25). for more information on this feature, see the tms320c645x dsp peripheral component interconnect (pci) user's guide (literature number sprue60 ) and the tms320c645x bootloader user's guide (literature number spruec6 ). table 7-96. default values for pci configuration registers default register value vendor id/device id register (pcivendev) 104c b000h class code/revision id register (pciclrev) 0000 0001h subsystem vendor id/subsystem id register 0000 0000h (pcisubid) max latency/min grant/interrupt pin/interrupt line 0000 0100h register (pcilgint) the on-chip bootloader supports a host boot which allows an external pci device to load application code into the dsp's memory space. the pci boot is terminated when the host generates a dsp interrupt. the host can generate a dsp interrupt through the pci peripheral by setting the dspint bit in the back-end application interrupt enable set register (pcibintset) and the status set register (pcistatset). for more information on the boot sequence of the c6454 dsp, see section 2.4 . note after the host boot is complete, the dsp interrupt is registered in bit 0 (channel 0) of the edma event register (er). this event must be cleared by software before triggering transfers on dma channel 0. submit documentation feedback c64x+ peripheral information and electrical specifications 207 product preview www.ti.com
7.16.2 pci peripheral register description(s) TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-97. pci configuration registers pci host access acronym pci host access register name hex address offset 0x00 pcivendev vendor id/device id 0x04 pcicsr command/status 0x08 pciclrev class code/revision id 0x0c pcicline bist/header type/latency timer/cacheline size 0x10 pcibar0 base address 0 0x14 pcibar1 base address 1 0x18 pcibar2 base address 2 0x1c pcibar3 base address 3 0x20 pcibar4 base address 4 0x24 pcibar5 base address 5 0x28 - 0x2b - reserved 0x2c pcisubid subsystem vendor id/subsystem id 0x30 - reserved 0x34 pcicpbptr capabilities pointer 0x38 - 0x3b - reserved 0x3c pcilgint max latency/min grant/interrupt pin/interrupt line 0x40 - 0x7f - reserved c64x+ peripheral information and electrical specifications 208 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-98. pci back end configuration registers dsp access acronym dsp access register name hex address range 02c0 0000 - 02c0 000f - reserved 02c0 0010 pcistatset pci status set register 02c0 0014 pcistatclr pci status clear register 02c0 0018 - 02c0 001f - reserved 02c0 0020 pcihintset pci host interrupt enable set register 02c0 0024 pcihintclr pci host interrupt enable clear register 02c0 0028 - 02c0 002f - reserved 02c0 0030 pcibintset pci back end application interrupt enable set register 02c0 0034 pcibintclr pci back end application interrupt enable clear register 02c0 0038 pcibclkmgt pci back end application clock management register 02c0 003c - 02c0 00ff - reserved 02c0 0100 pcivendevmir pci vendor id/device id mirror register 02c0 0104 pcicsrmir pci command/status mirror register 02c0 0108 pciclrevmir pci class code/revision id mirror register 02c0 010c pciclinemir pci bist/header type/latency timer/cacheline size mirror register 02c0 0110 pcibar0msk pci base address mask register 0 02c0 0114 pcibar1msk pci base address mask register 1 02c0 0118 pcibar2msk pci base address mask register 2 02c0 011c pcibar3msk pci base address mask register 3 02c0 0120 pcibar4msk pci base address mask register 4 02c0 0124 pcibar5msk pci base address mask register 5 02c0 0128 - 02c0 012b - reserved 02c0 012c pcisubidmir pci subsystem vendor id/subsystem id mirror register 02c0 0130 - reserved 02c0 0134 pcicpbptrmir pci capabilities pointer mirror register 02c0 0138 - 02c0 013b - reserved 02c0 013c pcilgintmir pci max latency/min grant/interrupt pin/interrupt line mirror register 02c0 0140 - 02c0 017f - reserved 02c0 0180 pcislvcntl pci slave control register 02c0 0184 - 02c0 01bf - reserved 02c0 01c0 pcibar0trl pci slave base address 0 translation register 02c0 01c4 pcibar1trl pci slave base address 1 translation register 02c0 01c8 pcibar2trl pci slave base address 2 translation register 02c0 01cc pcibar3trl pci slave base address 3 translation register 02c0 01d0 pcibar4trl pci slave base address 4 translation register 02c0 01d4 pcibar5trl pci slave base address 5 translation register 02c0 01d8 - 02c0 01df - reserved 02c0 01e0 pcibar0mir pci base address register 0 mirror register 02c0 01e4 pcibar1mir pci base address register 1 mirror register 02c0 01e8 pcibar2mir pci base address register 2 mirror register 02c0 01ec pcibar3mir pci base address register 3 mirror register 02c0 01f0 pcibar4mir pci base address register 4 mirror register 02c0 01f4 pcibar5mir pci base address register 5 mirror register 02c0 01f8 - 02c0 02ff - reserved 02c0 0300 pcimcfgdat pci master configuration/io access data register 02c0 0304 pcimcfgadr pci master configuration/io access address register submit documentation feedback c64x+ peripheral information and electrical specifications 209 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-98. pci back end configuration registers (continued) dsp access acronym dsp access register name hex address range 02c0 0308 pcimcfgcmd pci master configuration/io access command register 02c0 030c - 02c0 030f - reserved 02c0 0310 pcimstcfg pci master configuration register table 7-99. dsp-to_pci address translation registers dsp access acronym dsp access register name hex address range 02c0 0314 pciaddsub0 pci address substitute 0 register 02c0 0318 pciaddsub1 pci address substitute 1 register 02c0 031c pciaddsub2 pci address substitute 2 register 02c0 0320 pciaddsub3 pci address substitute 3 register 02c0 0324 pciaddsub4 pci address substitute 4 register 02c0 0328 pciaddsub5 pci address substitute 5 register 02c0 032c pciaddsub6 pci address substitute 6 register 02c0 0330 pciaddsub7 pci address substitute 7 register 02c0 0334 pciaddsub8 pci address substitute 8 register 02c0 0338 pciaddsub9 pci address substitute 9 register 02c0 033c pciaddsub10 pci address substitute 10 register 02c0 0340 pciaddsub11 pci address substitute 11 register 02c0 0344 pciaddsub12 pci address substitute 12 register 02c0 0348 pciaddsub13 pci address substitute 13 register 02c0 034c pciaddsub14 pci address substitute 14 register 02c0 0350 pciaddsub15 pci address substitute 15 register 02c0 0354 pciaddsub16 pci address substitute 16 register 02c0 0358 pciaddsub17 pci address substitute 17 register 02c0 035c pciaddsub18 pci address substitute 18 register 02c0 0360 pciaddsub19 pci address substitute 19 register 02c0 0364 pciaddsub20 pci address substitute 20 register 02c0 0368 pciaddsub21 pci address substitute 21 register 02c0 036c pciaddsub22 pci address substitute 22 register 02c0 0370 pciaddsub23 pci address substitute 23 register 02c0 0374 pciaddsub24 pci address substitute 24 register 02c0 0378 pciaddsub25 pci address substitute 25 register 02c0 037c pciaddsub26 pci address substitute 26 register 02c0 0380 pciaddsub27 pci address substitute 27 register 02c0 0384 pciaddsub28 pci address substitute 28 register 02c0 0388 pciaddsub29 pci address substitute 29 register 02c0 038c pciaddsub30 pci address substitute 30 register 02c0 0390 pciaddsub31 pci address substitute 31 register c64x+ peripheral information and electrical specifications 210 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-100. pci hook configuration registers dsp access acronym dsp access register name hex address range 02c0 0394 pcivendevprg pci vendor id and device id program register 02c0 0398 pcicmdstatprg pci command and status program register 02c0 039c pciclrevprg pci class code and revision id program register 02c0 03a0 pcisubidprg pci subsystem vendor id and subsystem id program register 02c0 03a4 pcimaxlgprg pci max latency and min grant program register 02c0 03a8 pcilrstreg pci lreset register 02c0 03ac pcicfgdone pci configuration done register 02c0 03b0 pcibar0mprg pci base address mask register 0 program register 02c0 03b4 pcibar1mprg pci base address mask register 1 program register 02c0 03b8 pcibar2mprg pci base address mask register 2 program register 02c0 03bc pcibar3mprg pci base address mask register 3 program register 02c0 03c0 pcibar4mprg pci base address mask register 4 program register 02c0 03c4 pcibar5mprg pci base address mask register 5 program register 02c0 03c8 pcibar0prg pci base address register 0 program register 02c0 03cc pcibar1prg pci base address register 1 program register 02c0 03d0 pcibar2prg pci base address register 2 program register 02c0 03d4 pcibar3prg pci base address register 3 program register 02c0 03d8 pcibar4prg pci base address register 4 program register 02c0 03dc pcibar5prg pci base address register 5 program register 02c0 03e0 pcibar0trlprg pci base address translation register 0 program register 02c0 03e4 pcibar1trlprg pci base address translation register 1 program register 02c0 03e8 pcibar2trlprg pci base address translation register 2 program register 02c0 03ec pcibar3trlprg pci base address translation register 3 program register 02c0 03f0 pcibar4trlprg pci base address translation register 4 program register 02c0 03f4 pcibar5trlprg pci base address translation register 5 program register 02c0 03f8 pcibasenprg pci base en prog register 02c0 03fc - 02c0 03ff - reserved table 7-101. pci external memory space hex address offset acronym register name 4000 0000 - 407f ffff - pci master window 0 4080 0000 - 40ff ffff - pci master window 1 4100 0000 - 417f ffff - pci master window 2 4180 0000 - 41ff ffff - pci master window 3 4200 0000 - 427f ffff - pci master window 4 4280 0000 - 42ff ffff - pci master window 5 4300 0000 - 437f ffff - pci master window 6 4380 0000 - 43ff ffff - pci master window 7 4400 0000 - 447f ffff - pci master window 8 4480 0000 - 44ff ffff - pci master window 9 4500 0000 - 457f ffff - pci master window 10 4580 0000 - 45ff ffff - pci master window 11 4600 0000 - 467f ffff - pci master window 12 4680 0000 - 46ff ffff - pci master window 13 4700 0000 - 477f ffff - pci master window 14 submit documentation feedback c64x+ peripheral information and electrical specifications 211 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-101. pci external memory space (continued) hex address offset acronym register name 4780 0000 - 47ff ffff - pci master window 15 4800 0000 - 487f ffff - pci master window 16 4880 0000 - 48ff ffff - pci master window 17 4900 0000 - 497f ffff - pci master window 18 4980 0000 - 49ff ffff - pci master window 19 4a00 0000 - 4a7f ffff - pci master window 20 4a80 0000 - 4aff ffff - pci master window 21 4b00 0000 - 4b7f ffff - pci master window 22 4b80 0000 - 4bff ffff - pci master window 23 4c00 0000 - 4c7f ffff - pci master window 24 4c80 0000 - 4cff ffff - pci master window 25 4d00 0000 - 4d7f ffff - pci master window 26 4d80 0000 - 4dff ffff - pci master window 27 4e00 0000 - 4e7f ffff - pci master window 28 4e80 0000 - 4eff ffff - pci master window 29 4f00 0000 - 4f7f ffff - pci master window 30 4f80 0000 - 4fff ffff - pci master window 31 c64x+ peripheral information and electrical specifications 212 submit documentation feedback www.ti.com product preview
7.16.3 pci electrical data/timing TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 texas instruments (ti) has performed the simulation and system characterization to ensure that the pci peripheral meets all ac timing specifications as required by the pci local bus specification (version 2.3). the ac timing specifications are not reproduced here. for more information on the ac timing specifications, see section 4.2.3, timing specification (33 mhz timing), and section 7.6.4, timing specification (66 mhz timing), of the pci local bus specification (version 2.3). note that the c6454 pci peripheral only supports 3.3-v signaling. submit documentation feedback c64x+ peripheral information and electrical specifications 213 product preview www.ti.com
7.17 general-purpose input/output (gpio) 7.17.1 gpio device-specific information 7.17.2 gpio peripheral register description(s) TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 on the c6454 the gpio peripheral pins gp[15:8] and gp[3:0] are muxed with the pci and mcbsp1 peripheral pins and the sysclk4 signal. for more detailed information on device/peripheral configuration and the c6454 device pin muxing, see section 3 , device configuration. table 7-102. gpio registers hex address range acronym register name 02b0 0008 binten gpio interrupt per bank enable register 02b0 000c - reserved 02b0 0010 dir gpio direction register 02b0 0014 out_data gpio output data register 02b0 0018 set_data gpio set data register 02b0 001c clr_data gpio clear data register 02b0 0020 in_data gpio input data register 02b0 0024 set_ris_trig gpio set rising edge interrupt register 02b0 0028 clr_ris_trig gpio clear rising edge interrupt register 02b0 002c set_fal_trig gpio set falling edge interrupt register 02b0 0030 clr_fal_trig gpio clear falling edge interrupt register 02b0 008c - reserved 02b0 0090 - 02b0 00ff - reserved 02b0 0100 - 02b0 3fff - reserved c64x+ peripheral information and electrical specifications 214 submit documentation feedback www.ti.com product preview
7.17.3 gpio electrical data/timing TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 7-103. timing requirements for gpio inputs (1) (2) (see figure 7-74 ) -720 -850 no. unit -1000 min max 1 t w(gpih) pulse duration, gpix high 12p ns 2 t w(gpil) pulse duration, gpix low 12p ns (1) p = 1/cpu clock frequency in ns. for example, when running parts at 1000 mhz, use p = 1 ns. (2) the pulse width given is sufficient to generate a cpu interrupt or an edma event. however, if a user wants to have the dsp recognize the gpix changes through software polling of the gpio register, the gpix duration must be extended to at least 12p to allow the dsp enough time to access the gpio register through the cfgbus. table 7-104. switching characteristics over recommended operating conditions for gpio outputs (1) (see figure 7-74 ) -720 -850 no. parameter unit -1000 min max 3 t w(gpoh) pulse duration, gpox high 36p ? 8 (2) ns 4 t w(gpol) pulse duration, gpox low 36p ? 8 (2) ns (1) p = 1/cpu clock frequency in ns. for example, when running parts at 1000 mhz, use p = 1 ns. (2) this parameter value should not be used as a maximum performance specification. actual performance of back-to-back accesses of the gpio is dependent upon internal bus activity. figure 7-74. gpio port timing submit documentation feedback c64x+ peripheral information and electrical specifications 215 product preview www.ti.com gpix gpox 4 3 2 1
7.18 ieee 1149.1 jtag 7.18.1 jtag device-specific information 7.18.2 jtag peripheral register description(s) 7.18.3 jtag electrical data/timing TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 7.18.1.1 ieee 1149.1 jtag compatibility statement for maximum reliability, the c6454 dsp includes an internal pulldown (ipd) on the trst pin to ensure that trst will always be asserted upon power up and the dsp's internal emulation logic will always be properly initialized when this pin is not routed out. jtag controllers from texas instruments actively drive trst high. however, some third-party jtag controllers may not drive trst high but expect the use of an external pullup resistor on trst. when using this type of jtag controller, assert trst to initialize the dsp after powerup and externally drive trst high before attempting any emulation or boundary scan operations. table 7-105. timing requirements for jtag test port (see figure 7-75 ) -720 -850 no. unit -1000 min max 1 t c(tck) cycle time, tck 35 ns 3 t su(tdiv-tckh) setup time, tdi/tms/ trst valid before tck high 10 ns 4 t h(tckh-tdiv) hold time, tdi/tms/ trst valid after tck high 9 ns table 7-106. switching characteristics over recommended operating conditions for jtag test port (see figure 7-75 ) -720 -850 no. parameter unit -1000 min max 2 t d(tckl-tdov) delay time, tck low to tdo valid -3 18 ns figure 7-75. jtag test-port timing 216 c64x+ peripheral information and electrical specifications submit documentation feedback www.ti.com product preview tck tdo tdi/tms/trst 1 2 3 4 2
8 mechanical data 8.1 thermal data 8.2 packaging information TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 table 8-1 shows the thermal resistance characteristics for the pbga - ztz/gtz mechanical package. table 8-1. thermal resistance characteristics (s-pbga package) [ztz/gtz] no. c/w air flow (m/s (1) ) 1 r q jc junction-to-case 1.45 n/a 2 r q jb junction-to-board 8.34 n/a 3 16.1 0.00 4 13.0 1.0 r q ja junction-to-free air 5 11.9 2.0 6 10.7 3.0 0.37 0.00 0.89 1.0 7 psi jt junction-to-package top 1.01 1.5 1.17 3.00 7.6 0.00 6.7 1.0 8 psi jb junction-to-board 6.4 1.5 5.8 3.00 (1) m/s = meters per second the following packaging information reflects the most current released data available for the designated device(s). this data is subject to change without notice and without revision of this document. submit documentation feedback mechanical data 217 product preview www.ti.com
revision history TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 this data sheet revision history highlights the technical changes made to the sprs311 device-specific data sheet to make it an sprs311a revision. scope: applicable updates to the c64x device family, specifically relating to the TMS320C6454 device, have been incorporated. c6454 revision history see additions/modifications/deletions global changed ddr2 memory controller speed to 533 mhz changed l2 memory size to 1048kb section 1.1 features: changed emifa bullet to 64-bit external memory interface (emifa) added 1.25-v internal section 1.1.1 change section title to ztz /gtz bga package (bottom view): added gtz to section 1.1.1 , ztz/gtz bga package (bottom view) section 1.3 functional block diagram: updated figure 1-2 , functional block diagram section 2.1 device characteristics: table 2-1 , characteristics of the c6454 processor: deleted [133 mhz] from emifa (64-bit bus width) changed on-chip memory size to 1144k updated core voltages updated megamodule revision id updated jtag bsdl_id added gtz package section 2.3 memory map summary: added edma transfer controller 0-3 registers to table 2-2 , c6454 memory map summary section 2.4.1 boot modes supported: updated paragraphs under host boot bullet replaced tbd document reference with tms320c645x bootloader user's guide (literature number spruec6 ) section 2.5.1 pin map: updated figure 2-4 , c6454 pin map (bottom view) [quadrant c] and figure 2-5 , c6454 pin map (bottom view) [quadrant d] section 2.6 signal groups description: updated figure 2-6 , cpu and peripheral signals table 2-3 terminal functions: updated footnote (2) added footnote (5) reference to signals pserr and pinta updated signal description for ar/ w updated signal description for deodt1 and deodt2 updated signal descriptions for rsv07, rsv09, rsv15, rsv16, rsv32, rsv33, rsv34, and rsv35 changed signal n1 to cv ddmon , updated description, and moved under supply voltage monitor pins changed signal l6 to dv dd33mon , updated description, and moved under supply voltage monitor pins changed signal f3 to dv dd15mon , updated description, and moved under supply voltage monitor pins changed signal a26 to dv dd18mon , updated description, and moved under supply voltage monitor pins updated descriptions for signals av dda , dv ddrm , dv dd12 , av ddt , and cv dd section 2.8.2.1 device and development-support tool nomenclature: updated figure 2-12 , tms320c64x+ dsp device nomenclature (including the TMS320C6454 dsp) section 2.8.2.2 documentation support: updated list of related documentation section 3.1 device configuration at device reset: updated paragraph and note updated footnote (1) and configuration pin aea3 description in table 3-1 , c6454 device configuration pins (aea[19:0], aba[1:0], and pci_en) section 3.3 peripheral selection after device reset: updated table 3-4 , peripheral states added note section 3.4.1 peripheral lock register description: added note revision history 218 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 c6454 revision history (continued) see additions/modifications/deletions section 3.4.2 peripheral configuration register 0 description: updated paragraph and added note changed all bit field resets to r/w-0 and updated figure 3-4 , peripheral configuration register 0 (percfg0) updated table 3-7 , peripheral configuration register 0 (percfg0) field descriptions section 3.4.5 emac configuration register (emaccfg) description: changed bits 23:19 reset value to r/w- 0001b and moved in rmii_rst field to bit 18 figure 3-8 , emac configuration register (emaccfg) updated reserved bits 31:19 description and rmii_rst bit 18 description values 0 and 1 in table 3-11 , emac configuration register (emaccfg) field descriptions section 3.7 deleted debugging considerations added new section, pullup/pulldown resistors section 3.8 configuration examples: added comments for aea[12], aea[11], and aea[3] and changed sysclk3 to sysclk 4 in comment for aea[4] in figure 3-12 , configuration example a, and figure 3-13 , configuration example b section 5.1 memory architecture: updated paragraphs updated figure 5-4 , TMS320C6454 l2 memory configurations section 6 device operating conditions: updated section 6.1 , absolute maximum ratings over operating case temperature range updated section 6.2 , recommended operating conditions updated section 6.3 , electrical characteristics over recommended ranges of supply voltage and operating case temperature section 7.3.1 power-supply sequencing: updated paragraph deleted power-supply sequence (option 1) figure and timing requirements for power-supply sequence (option 1) table section 7.3.4 preserving boundary-scan functionality on rgmii and ddr2 memory pins section: added dv dd15mon to paragraph and list section 7.4 enhanced direct memory access (edma3) controller: changed "4 quick dma (qdma) channels" to " 8 quick dma (qdma) channels" section 7.4.1 edma3 device-specific information: updated paragraph section 7.4.3 edma3 peripheral register description(s): changed table 7-4 title to edma3 channel controller registers updated hex address ranges for parameter sets 7, 9, 254, and 255 on table 7-5 , edma3 parameter ram added table 7-6 , edma3 transfer controller 0 registers, table 7-7 , edma3 transfer controller 1 registers, table 7-8 , edma3 transfer controller 2 registers, and table 7-9 , edma3 transfer controller 3 registers section 7.5.1 interrupt sources and interrupt controller: changed event number 80 to reserved in table 7-10 , c6454 dsp interrupts section 7.6 reset controller: updated system reset effect(s), and added footnote (2) in table 7-12 , reset types deleted system reset timing figure section 7.6.7 reset electrical data/timing: updated note added new footnote (3) and renumbered footnotes to (4) and (5) in table 7-14 , timing requirements for reset section 7.7 pll1 and pll1 controller: updated figure 7-10 , pll1 and pll1 controller section 7.7.1 pll1 controller device-specific information: updated sysclk4 bullet updated paragraphs updated footnote (1) in table 7-16 , pll1 clock frequency ranges submit documentation feedback revision history 219 product preview www.ti.com
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 c6454 revision history (continued) see additions/modifications/deletions section 7.7.3 pll1 controller register descriptions: added values and descriptions for ratio bit field in table 7-21 , pll pre-divider control register (prediv) field descriptions deleted pll controller divider registers section added new sections for pll controller divider 4 register and pll controller divider 5 register change ratio bit field reset to r/w- 3 in figure 7-14 , pll controller divider 4 register (plldiv4) changed ratio bit field reset to r/w- 3 in figure 7-15 , pll controller divider 5 register (plldiv5) section 7.7.4 pll1 controller input and output clock electrical data/timing: updated figure 7-22 , sysclk4 timing section 7.8 pll2 and pll2 controller: updated notes a and b on figure 7-23 , pll2 block diagram section 7.8.1 pll2 controller device-specific information: updated footnote (1) in table 7-31 , pll2 clock frequency ranges section 7.8.1.1 internal clocks and maximum operating frequencies: updated paragraphs section 7.8.4 pll2 controller input clock electrical data/timing: updated footnote (3) in table 7-39 , timing requirements for clkin2 section 7.9 ddr2 memory controller: updated paragraphs section 7.10.2 emifa peripheral register description(s): changed burst priority register acronym to burst_prio in table 7-41 , emifa registers section 7.10.3 emifa electrical data/timing: updated footnotes for table 7-45 , table 7-47 and figure 7-33 , figure 7-36 , figure 7-37 , and figure 7-38 updated figure 7-34 , asynchronous memory write timing for emifa section 7.12.2 hpi peripheral register description(s): updated comments for hpic in table 7-54 , hpi control registers updated hex address and comments for hpia registers added footnote (1) updated footnote (2) section 7.12.3 hpi electrical data/timing: changed parameter no. 18 min value to 1 ns and parameter no. 38 min value to 1.1 ns in table 7-55 , timing requirements for host-port interface cycles replaced tbd document reference with tms320c645x dsp host port interface user's guide (literature number spru969 ) in figure 7-44 through figure 7-51 section 7.13.1 mcbsp device-specific information: added paragraph section 7.13.2 mcbsp electrical data/timing: changed parameter no. 4 max value to 3.3 ns in table 7-60 , switching characteristics over recommended operating conditions for mcbsp section 7.14.1 emac device-specific information: deleted step 1 and changed setting to clearing under using the rmii mode of the emac moved table 7-70 , emac/mdio multiplexed pins (mii, rmii, and gmii modes), under interface mode select added interface mode clocking section and paragraphs section 7.14.2 emac peripheral register description(s): corrected hex addresses for 02c8 0 080 through 02c8 0 090 in table 7-71 , ethernet mac (emac) control registers section 7.14.3.1 emac mii and gmii electrical data/timing: updated figure 7-59 , mrclk timing (emac ? receive) [mii and gmii operation] updated figure 7-60 , mtclk timing (emac ? transmit) [mii and gmii operation] changed table 7-77 title to switching characteristics over recommended operating conditions for gmtclk - gmii operation updated figure 7-61 , gmtclk timing (emac ? transmit) [gmii operation] updated figure 7-64 , emac transmit interface timing [gmii operation] section 7.14.3.2 emac rmii electrical data/timing: added the following tables and figures: table 7-82 , switching characteristics over recommended operating conditions for emac rmii transmit 10/100 mbit/s figure 7-66 , emac transmit interface timing [rmii operation] table 7-83 , timing requirements for emac rmii input receive for 100 mbps figure 7-67 , emac receive interface timing [rmii operation] revision history 220 submit documentation feedback www.ti.com product preview
TMS320C6454 fixed-point digital signal processor sprs311a ? april 2006 ? revised december 2006 c6454 revision history (continued) see additions/modifications/deletions section 7.14.3.3 emac rgmii electrical data/timing: updated table 7-84 , switching characteristics over recommended operating conditions for emac rgrefclk - rgmii operation updated figure 7-68 , rgrefclk timing changed table 7-87 title to switching characteristics over recommended operating conditions for txc - rgmii operation for 10/100/100 mbit/s section 7.14.4.1 mdio device-specific information: updated paragraph section 7.16.1 pci device-specific information: updated paragraphs added table 7-96 , default values for pci configuration registers section 7.16.3 pci electrical data/timing: deleted peripheral component interconnect (pci) timing section added new paragraph section 8 mechanical data: added the gtz (s-pbga-n697) plastic ball grid array mechanical package drawing submit documentation feedback revision history 221 product preview www.ti.com
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) TMS320C6454bztz active fcbga ztz 697 44 pb-free (rohs exempt) snagcu level-4-260c-72hr TMS320C6454bztz7 active fcbga ztz 697 44 pb-free (rohs exempt) snagcu level-4-260c-72hr TMS320C6454bztz8 active fcbga ztz 697 44 pb-free (rohs exempt) snagcu level-4-260c-72hr (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 7-dec-2006 addendum-page 1

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